FPGA Project Description for the Clock and Control Board CCB2004

1. Hardware Environment

- Xilinx XC2V250-4FG456 FPGA residing on the main CCB2004 board
- One XC18V02 PROM residing on the main CCB2004 board
- PROM can be reprogrammed via either VME or 
  JTAG connector on the front panel

2. FPGA i/o, data format, address space

- i/o's are listed in the UCF file ccb.ucf
- data formats for all registers are described in the
  CCB2004 specification
- address space (A24D16) for the FPGA: 680020...6800A2(hex)
  in the peripheral crate; 600020..6000A2(hex) in the 
  Track Finder crate.

3. FPGA model and vendor:

- Xilinx ISE 6.2.03
- ModelSim XE II 5.7g

4. Design Entry

- Xilinx ISE schematic and VHDL

5. Clocking

- 40MHz CLOCK_TTC (pin B11) provided by the TTCrq mezzanine card
- 80MHz CLOCK_80 (pin Y11) provided by either TTCrq mezzanine or
  on-board 80MHz oscillator (optional)
- 16MHz CLOCK_VME (pin D11) from the VME backplane (optional)
- 40MHz CLOCK_Q (pin F12) from the on-board oscillator (CLOCK_80
  divided by two) (optional)

6. General Description

The FPGA performs command generation and distribution to 
custom backplane under VME control. See CCB2004 specification 
for more details.

7. Verification

None.