FPGA Project Description for the Muon Port Card MPC2004 1. Hardware Environment - Xilinx XCV600E-8FG680C FPGA residing on a mezzanine board - One XC18V04 PROM residing on the same mezzanine - PROM can be reprogrammed via either VME or JTAG connector on the front panel 2. FPGA i/o, data format, address space - i/o's are listed in the UCF file mpc1.ucf - data formats for all registers are described in the MPC2004 specification - address space (A24D16) for the FPGA: 600080...6000CE(hex) 3. FPGA model and vendor: - Xilinx ISE 6.2.03 - ModelSim XE II 5.7g 4. Design Entry - Xilinx ISE schematic and VHDL 5. Clocking - 40MHz CLOCK40CCB (pin A20) provided by the Clock and Control Board via custom backplane 6. General Description The FPGA performs sorting "3 best patterns out of 18", pattern transmission to the TLK2501 serializer residing on the main MPC2004 board. More details are available in the MPC2004 specification. 7. Verification - testbench VHDL file for sorter verification is included in the project