FPGA Project Description for the Muon Sorter MS2005 Board

1. Hardware Environment

- Xilinx XC2V4000-5FF1152C FPGA residing on a mezzanine board
- Four XC18V04 PROMs residing on the same mezzanine
- FPGA and PROMs can be loaded/reprogrammed via either VME or 
  JTAG connector P10 on the main board

2. FPGA i/o, data format, address space

- i/o's are listed in the UCF file ms1.ucf
- data formats for all registers are described in the
  MS2005 specification
- address space (A24D16) for the FPGA: 700100...7013FE(hex)

3. FPGA model and vendor:

- Xilinx ISE 6.2.03
- ModelSim XE II 5.7g

4. Design Entry

- Xilinx ISE schematic and VHDL

5. Clocking

- 40MHz CLKMS (pin AK17) provided by the Clock and Control Board
- 16MHZ CLKVME (pin AK19) provided from the VME backplane (optional)

6. General Description

The FPGA performs sorting "4 best patterns out of 36",
partial LUT conversion and pattern transmission to the
Global Muon Trigger (GMT) receiver board. More details
are available in the MS2005 specification.

7. Verification

- testbench VHDL file for sorter verification is included in the project