PLD Project Description for the Muon Sorter MS2005 Board

1. Hardware Environment

- Xilinx XCR3128XL PLD residing on the main MS2005 board
- PLD can be reprogrammed via JTAG connector P11 on the main board

2. PLD i/o, data format, address space

- i/o's are listed in the UCF file msvme.ucf
- data formats for all registers are described in the
  MS2005 specification
- address space (A24D16) for the PLD: 700000...700018(hex)

3. PLD model and vendor:

- Xilinx ISE 6.2.03

4. Design Entry

- Xilinx ISE schematic and VHDL

5. Clocking

- 40MHz CLOCK_CCB (pin 128) provided by the Clock and Control Board
  via custom backplane
- 16MHZ CLOCK_VME (pin 127) provided from the VME backplane

6. General Description

The PLD performs two main functions for the MS2005 boards:
- VME DS/DACK handshake logic
- control of the JTAG SCANPSC100 controller which allows
  to access the FPGA and PROMs on a mezzanine board

7. Verification

None.