// read IDCODE/USERCODE from the XC2V250 FPGA and XC18V02 EPROM on CCB2004 board
// JTAG chain: TDI -> XC18V02 -> TDO -> TDI -> XC2V250 -> TDO
// CCB2004 in slot 13 (peripheral crate, base address 680000hex)
// CSRA1: bit_5 = tdi, bit_6 = tms, bit_7 = tck, bit_8 = tdo

// soft reset CCB2004
	vme->Write((bt_devaddr_t)0x680004, (WORD)0x0);

// READ IDCODE/USERCODE FROM THE FPGA XC2V250; bypass XC18V02 EPROM

// set test_logic/reset mode 5 times

	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
        vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set run_test/idle mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set select_dr_scan mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set select_ir_scan mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set capture_ir_scan mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir_scan mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// read idcode instruction = 001001 from xc2v250 fpga
// read usercode instruction = 001000 from xc2v250 fpga

// set instruction bit 0
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 5 
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// bypass eprom
// send instruction = ff(hex) = bypass prom

// set instruction bit 0
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 5
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 6
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 7 + tms=1
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0060);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00e0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0060);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set update_ir
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set select_dr_scan
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set capture_dr
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_1 // not a part of IDCODE
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da2=Data&0x0100;
        Da2 = Da2 >> 8;
        vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	
// set shift_ir bit_2
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da3=Data&0x0100;
	Da3 = Da3 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_3
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da4=Data&0x0100;
	Da4 = Da4 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_4
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da5=Data&0x0100;
	Da5 = Da5 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	
// set shift_ir bit_5
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da6=Data&0x0100;
	Da6 = Da6 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
 
// set shift_ir bit_6
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da7=Data&0x0100;
	Da7 = Da7 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_7
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da8=Data&0x0100;
	Da8 = Da8 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_8
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da9=Data&0x0100;
	Da9 = Da9 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_9
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da10=Data&0x0100;
	Da10 = Da10 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_10
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da11=Data&0x0100;
	Da11 = Da11 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_11
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da12=Data&0x0100;
	Da12 = Da12 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_12
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da13=Data&0x0100;
	Da13 = Da13 >> 8;
 	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_13
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da14=Data&0x0100;
	Da14 = Da14 >>8;
 	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_14
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da15=Data&0x0100;
	Da15 = Da15 >>8;
 	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_15
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da16=Data&0x0100;
	Da16 = Da16 >>8;
 	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_16
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da17=Data&0x0100;
	Da17 = Da17 >>8;
 	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_17
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da18=Data&0x0100;
	Da18 = Da18 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_18
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da19=Data&0x0100;
	Da19 = Da19 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_19
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da20=Data&0x0100;
	Da20 = Da20 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_20
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da21=Data&0x0100;
	Da21 = Da21 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_21
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da22=Data&0x0100;
	Da22 = Da22 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_22
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da23=Data&0x0100;
	Da23 = Da23 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_23
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da24=Data&0x0100;
	Da24 = Da24 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_24
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da25=Data&0x0100;
	Da25 = Da25 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_25
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da26=Data&0x0100;
	Da26 = Da26 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_26
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da27=Data&0x0100;
	Da27 = Da27 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_27
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da28=Data&0x0100;
	Da28 = Da28 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_28
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da29=Data&0x0100;
	Da29 = Da29 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_29
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da30=Data&0x0100;
	Da30 = Da30 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_30
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da31=Data&0x0100;
	Da31 = Da31 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_31
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da32=Data&0x0100;
	Da32 = Da32 >>8;
        vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_32
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da33=Data&0x0100;
	Da33 = Da33 >>8;
        vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

	cout << " XC2V250 IDCODE = " << Da33 << Da32 << Da31 << Da30 << Da29 << Da28 << Da27 << Da26 << "_"	
	<< Da25 << Da24 << Da23 << Da22 << Da21 << Da20 << Da19 << Da18 << "_"	
	<< Da17 << Da16 << Da15 << Da14 << Da13 << Da12 << Da11 << Da10 << "_"	
	<< Da9 << Da8 << Da7 << Da6 << Da5 << Da4 << Da3 << Da2 <<endl;	

// set updata_dr
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// end read back an idcode from XC2V250 FPGA

 
// read IDCODE from xilinx XC18V02 EPROM

// set test_logic/reset mode 5 times

	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
        vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set run_test/idle mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set select_dr_scan mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set select_ir_scan mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set capture_ir_scan mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir_scan mode
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// send bypass instruction "111111" to FPGA XC2V250

// set instruction bit 0
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 5
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// send instruction = fe(hex) = idcode to eprom

// set instruction bit 0
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 5
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 6
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0020);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set instruction bit 7 + tms = 1
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0060);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00e0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0060);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set update_ir
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set select_dr_scan
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set capture_dr
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_0 // not a part of IDCODE
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da1=Data&0x0100;
	Da1 = Da1 >> 8;
 	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_1
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da2=Data&0x0100;
        Da2 = Da2 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_2
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da3=Data&0x0100;
	Da3 = Da3 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_3
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da4=Data&0x0100;
	Da4 = Da4 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_4
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da5=Data&0x0100;
	Da5 = Da5 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	
// set shift_ir bit_5
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da6=Data&0x0100;
	Da6 = Da6 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_6
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da7=Data&0x0100;
	Da7 = Da7 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_7
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da8=Data&0x0100;
	Da8 = Da8 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_8
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da9=Data&0x0100;
	Da9 = Da9 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_9
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da10=Data&0x0100;
	Da10 = Da10 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_10
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da11=Data&0x0100;
	Da11 = Da11 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_11
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da12=Data&0x0100;
	Da12 = Da12 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_12
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da13=Data&0x0100;
	Da13 = Da13 >> 8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_13
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da14=Data&0x0100;
	Da14 = Da14 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_14
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da15=Data&0x0100;
	Da15 = Da15 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_15
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da16=Data&0x0100;
	Da16 = Da16 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_16
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da17=Data&0x0100;
	Da17 = Da17 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_17
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da18=Data&0x0100;
	Da18 = Da18 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_18
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da19=Data&0x0100;
	Da19 = Da19 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_19
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da20=Data&0x0100;
	Da20 = Da20 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_20
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da21=Data&0x0100;
	Da21 = Da21 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_21
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da22=Data&0x0100;
	Da22 = Da22 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_22
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da23=Data&0x0100;
	Da23 = Da23 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_23
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da24=Data&0x0100;
	Da24 = Da24 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_24
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da25=Data&0x0100;
	Da25 = Da25 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_25
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da26=Data&0x0100;
	Da26 = Da26 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_26
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da27=Data&0x0100;
	Da27 = Da27 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_27
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da28=Data&0x0100;
	Da28 = Da28 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_28
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da29=Data&0x0100;
	Da29 = Da29 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_29
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
  	Da30=Data&0x0100;
	Da30 = Da30 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_30
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da31=Data&0x0100;
	Da31 = Da31 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_31
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da32=Data&0x0100;
	Da32 = Da32 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// set shift_ir bit_32
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0080);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);
        vme->Read((bt_devaddr_t)0x680000, (WORD*)&Data);
 	Da33=Data&0x0100;
	Da33 = Da33 >>8;
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

	cout << " XC18V02 IDCODE = " << Da33 << Da32 << Da31 << Da30 << Da29 << Da28 << Da27 << Da26 << "_"	
	<< Da25 << Da24 << Da23 << Da22 << Da21 << Da20 << Da19 << Da18 << "_"	
	<< Da17 << Da16 << Da15 << Da14 << Da13 << Da12 << Da11 << Da10 << "_"	
	<< Da9 << Da8 << Da7 << Da6 << Da5 << Da4 << Da3 << Da2 <<endl;	

// set updata_dr
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x00c0);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0040);
	vme->Write((bt_devaddr_t)0x680000, (WORD)0x0000);

// end read back an idcode from xc18v02 eprom