ccb2004 Project Status
Project File:	ccb2004.ise	Current State:	Programming File Generated
Module Name:	ccb	Errors:	No Errors
Target Device:	xc2v250-4fg456	Warnings:	301 Warnings
Product Version:	ISE 10.1.03 - Foundation Simulator	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

 

ccb2004 Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	1,471	3,072	47%
Number of 4 input LUTs	999	3,072	32%
Logic Distribution
Number of occupied Slices	1,534	1,536	99%
Number of Slices containing only related logic	1,350	1,534	88%
Number of Slices containing unrelated logic	184	1,534	11%
Total Number of 4 input LUTs	1,242	3,072	40%
Number used as logic	984
Number used as a route-thru	243
Number used as Shift registers	15
Number of bonded IOBs
Number of bonded	190	200	95%
IOB Flip Flops	22
Number of BUFGMUXs	7	16	43%
Number of DCMs	1	8	12%
Number of RPM macros	18

 

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri Mar 6 12:45:35 2015	0	250 Warnings	1 Info
Translation Report	Current	Fri Mar 6 12:45:50 2015	0	0	2 Infos
Map Report	Current	Fri Mar 6 12:46:08 2015	0	40 Warnings	2 Infos
Place and Route Report	Current	Fri Mar 6 12:46:49 2015	0	11 Warnings	2 Infos
Static Timing Report	Current	Fri Mar 6 12:46:57 2015	0	0	2 Infos
Bitgen Report	Current	Fri Mar 6 12:47:12 2015	0	37 Warnings	1 Info

Date Generated: 07/12/2016 - 12:16:35