ccb2004 Project Status (03/04/2016 - 14:51:30)
Project File: ccb2004.ise Current State: Programming File Generated
Module Name: ccb
  • Errors:
No Errors
Target Device: xc2v250-4fg456
  • Warnings:
248 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
ccb2004 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,466 3,072 47%  
Number of 4 input LUTs 998 3,072 32%  
Logic Distribution     
Number of occupied Slices 1,534 1,536 99%  
    Number of Slices containing only related logic 1,343 1,534 87%  
    Number of Slices containing unrelated logic 191 1,534 12%  
Total Number of 4 input LUTs 1,241 3,072 40%  
    Number used as logic 983      
    Number used as a route-thru 243      
    Number used as Shift registers 15      
Number of bonded IOBs
Number of bonded 188 200 94%  
    IOB Flip Flops 27      
Number of BUFGMUXs 7 16 43%  
Number of DCMs 1 8 12%  
Number of RPM macros 18      
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Mar 4 14:49:24 20160198 Warnings1 Info
Translation ReportCurrentFri Mar 4 14:49:45 2016002 Infos
Map ReportCurrentFri Mar 4 14:50:08 2016042 Warnings2 Infos
Place and Route ReportCurrentFri Mar 4 14:51:01 201608 Warnings2 Infos
Static Timing ReportCurrentFri Mar 4 14:51:11 2016002 Infos
Bitgen ReportCurrentFri Mar 4 14:51:29 2016037 Warnings1 Info

Date Generated: 03/04/2016 - 14:51:30