ccb2004 Project Status
Project File: ccb2004.ise Current State: Programming File Generated
Module Name: ccb
  • Errors:
No Errors
Target Device: xc2v250-4fg456
  • Warnings:
250 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
ccb2004 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,474 3,072 47%  
Number of 4 input LUTs 1,006 3,072 32%  
Logic Distribution     
Number of occupied Slices 1,534 1,536 99%  
    Number of Slices containing only related logic 1,337 1,534 87%  
    Number of Slices containing unrelated logic 197 1,534 12%  
Total Number of 4 input LUTs 1,249 3,072 40%  
    Number used as logic 990      
    Number used as a route-thru 243      
    Number used as Shift registers 16      
Number of bonded IOBs
Number of bonded 188 200 94%  
    IOB Flip Flops 27      
Number of BUFGMUXs 7 16 43%  
Number of DCMs 1 8 12%  
Number of RPM macros 18      
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Apr 29 12:22:54 20160200 Warnings1 Info
Translation ReportCurrentFri Apr 29 12:23:15 2016002 Infos
Map ReportCurrentFri Apr 29 12:23:38 2016043 Warnings2 Infos
Place and Route ReportCurrentFri Apr 29 12:24:23 201607 Warnings2 Infos
Static Timing ReportCurrentFri Apr 29 12:24:33 2016002 Infos
Bitgen ReportCurrentFri Apr 29 12:24:49 2016038 Warnings1 Info

Date Generated: 07/12/2016 - 11:58:06