// init; ODMB in slot 17
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);

// set CS=0 for the selected ADC
// FFFE - ADC1 (U30); FFFD - ADC2 (U31); FFFB - ADC3 (U32); FFF7 - ADC4 (U33);
// FFEF - ADC5 (U34); FFDF - ADC6 (U35); FFBF - ADC7 (U36);
vme->Write((bt_devaddr_t)0x88007c, (WORD)0xFFFE);

// start bit
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x2);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x3);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x2);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);

// select a channel CH0-CH7 of the chosen ADC (channel 0 below)
// SEL2
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
// SEL1
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
// SEL0
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);

// select full scale 0-10V
// RNG=1
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x2);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x3);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x2);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
// BIP=0
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);

// normal mode, external clock mode
// PD1=0
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
// PD0=1
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x2);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x3);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x2);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);

// generate 4 external clocks
// clock 9
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
// clock 10
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
// clock 11
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
// clock 12
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);

// read MSB bit 11 on a falling edge of the 5th clock
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 11 = "  << Data1 <<  endl;	

// read bit 10
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 10 = "  << Data1 <<  endl;	

// read bit 9
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 9 = "  << Data1 <<  endl;	

// read bit 8
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 8 = "  << Data1 <<  endl;	

// read bit 7
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 7 = "  << Data1 <<  endl;	

// read bit 6
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 6 = "  << Data1 <<  endl;	

// read bit 5
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 5 = "  << Data1 <<  endl;	

// read bit 4
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 4 = "  << Data1 <<  endl;	

// read bit 3
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 3 = "  << Data1 <<  endl;	

// read bit 2
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 2 = "  << Data1 <<  endl;	

// read bit 1
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 1 = "  << Data1 <<  endl;	

// read bit 0
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x1);
vme->Write((bt_devaddr_t)0x88007a, (WORD)0x0);
vme->Read((bt_devaddr_t)0x880004, (WORD*)&Data);
Data1=Data&0x0001;
cout << hex << " Bit 0 = "  << Data1 <<  endl;	

// set CS=1
vme->Write((bt_devaddr_t)0x88007c, (WORD)0xFFFF);

// end reading the lvmb