mpc1 Project Status (11/28/2017 - 11:09:17)
Project File: mpc1.xise Parser Errors: No Errors
Module Name: mpc1 Implementation State: Programming File Generated
Target Device: xc6slx150t-3fgg900
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
970 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 12,032 184,304 6%  
    Number used as Flip Flops 12,022      
    Number used as Latches 10      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 9,675 92,152 10%  
    Number used as logic 8,434 92,152 9%  
        Number using O6 output only 5,603      
        Number using O5 output only 469      
        Number using O5 and O6 2,362      
        Number used as ROM 0      
    Number used as Memory 149 21,680 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 149      
            Number using O6 output only 1      
            Number using O5 output only 0      
            Number using O5 and O6 148      
    Number used exclusively as route-thrus 1,092      
        Number with same-slice register load 1,057      
        Number with same-slice carry load 35      
        Number with other load 0      
Number of occupied Slices 4,582 23,038 19%  
Number of MUXCYs used 2,868 46,076 6%  
Number of LUT Flip Flop pairs used 13,242      
    Number with an unused Flip Flop 3,677 13,242 27%  
    Number with an unused LUT 3,567 13,242 26%  
    Number of fully used LUT-FF pairs 5,998 13,242 45%  
    Number of unique control sets 677      
    Number of slice register sites lost
        to control set restrictions
3,759 184,304 2%  
Number of bonded IOBs 507 540 93%  
    Number of LOCed IOBs 507 507 100%  
    IOB Flip Flops 411      
    IOB Master Pads 5      
    IOB Slave Pads 5      
    Number of bonded IPADs 4 32 12%  
        Number of LOCed IPADs 4 4 100%  
    Number of bonded OPADs 16 16 100%  
        Number of LOCed OPADs 16 16 100%  
Number of RAMB16BWERs 0 268 0%  
Number of RAMB8BWERs 58 536 10%  
Number of BUFIO2/BUFIO2_2CLKs 4 32 12%  
    Number used as BUFIO2s 4      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 3 32 9%  
    Number used as BUFIO2FBs 3      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 12 16 75%  
    Number used as BUFGs 12      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 4 12 33%  
    Number used as DCMs 4      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 338 586 57%  
    Number used as ILOGIC2s 338      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 586 0%  
Number of OLOGIC2/OSERDES2s 72 586 12%  
    Number used as OLOGIC2s 72      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 180 0%  
Number of GTPA1_DUALs 4 4 100%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCIE_A1s 0 1 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 6 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.05      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Nov 28 11:03:44 20170937 Warnings (1 new)164 Infos (162 new)
Translation ReportCurrentTue Nov 28 11:03:56 201701 Warning (0 new)0
Map ReportCurrentTue Nov 28 11:06:48 2017019 Warnings (0 new)9 Infos (0 new)
Place and Route ReportCurrentTue Nov 28 11:08:13 201707 Warnings (0 new)0
Static Timing ReportCurrentTue Nov 28 11:08:29 2017003 Infos (0 new)
Bitgen ReportCurrentTue Nov 28 11:09:09 201706 Warnings (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Nov 28 11:09:11 2017
WebTalk Log FileCurrentTue Nov 28 11:09:15 2017

Date Generated: 11/29/2017 - 08:32:39