Project Statistics |
PROPEXT_xilxMapPackRegInto_spartan6=For Inputs and Outputs |
PROP_CompxlibOverwriteLib=true |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PostTrceFastPath=false |
PROP_PreTrceFastPath=false |
PROP_PropSpecInProjFile=Store all values |
PROP_ReduceControlSets_spartan6=No |
PROP_SelectedInstanceHierarchicalPath=/testbench/uut |
PROP_SimModelInsertBuffersPulseSwallow=false |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthOptEffort=High |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=Schematic |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2011-02-04T13:02:17 |
PROP_intWbtProjectID=5791F61FD98743B7987AE3F307838D55 |
PROP_intWbtProjectIteration=14 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.mpc1 |
PROP_xilxBitgCfg_Code=0x04122017 |
PROP_xilxBitgCfg_EnableExternalMasterClk_spartan6=true |
PROP_xilxBitgCfg_GenOpt_Compress=true |
PROP_xilxBitgCfg_Rate_spartan6=26 |
PROP_xilxBitgSusWake_EnGlblSetReset_spartan6=true |
PROP_xilxMapCoverMode=Speed |
PROP_xilxNgdbldIOPads=true |
PROP_xstCrossClockAnalysis=true |
PROP_xstEquivRegRemoval=false |
PROP_xstLUTCombining_spartan6=No |
PROP_xstPackIORegister=Yes |
PROP_AutoTop=true |
PROP_CompxlibSmartModels=true |
PROP_DevFamily=Spartan6 |
PROP_MapExtraEffort_spartan6=Normal |
PROP_MapRegDuplication_spartan6=On |
PROP_xilxBitgCfg_GenOpt_BinaryFile=true |
PROPEXT_xilxPARextraEffortLevel_spartan6=Normal |
PROP_CompxlibSimPath=changed |
PROP_DevDevice=xc6slx150t |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=fgg900 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=VHDL |
FILE_COREGEN=5 |
FILE_SCHEMATIC=1 |
FILE_UCF=1 |
FILE_VERILOG=4 |
FILE_VHDL=41 |