Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
10,593 |
184,304 |
5% |
|
Number used as Flip Flops |
10,582 |
|
|
|
Number used as Latches |
11 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
0 |
|
|
|
Number of Slice LUTs |
9,418 |
92,152 |
10% |
|
Number used as logic |
8,463 |
92,152 |
9% |
|
Number using O6 output only |
6,265 |
|
|
|
Number using O5 output only |
452 |
|
|
|
Number using O5 and O6 |
1,746 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
57 |
21,680 |
1% |
|
Number used as Dual Port RAM |
0 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
57 |
|
|
|
Number using O6 output only |
48 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
9 |
|
|
|
Number used exclusively as route-thrus |
898 |
|
|
|
Number with same-slice register load |
860 |
|
|
|
Number with same-slice carry load |
38 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
4,168 |
23,038 |
18% |
|
Number of MUXCYs used |
2,264 |
46,076 |
4% |
|
Number of LUT Flip Flop pairs used |
12,222 |
|
|
|
Number with an unused Flip Flop |
3,502 |
12,222 |
28% |
|
Number with an unused LUT |
2,804 |
12,222 |
22% |
|
Number of fully used LUT-FF pairs |
5,916 |
12,222 |
48% |
|
Number of unique control sets |
595 |
|
|
|
Number of slice register sites lost to control set restrictions |
3,277 |
184,304 |
1% |
|
Number of bonded IOBs |
509 |
540 |
94% |
|
Number of LOCed IOBs |
509 |
509 |
100% |
|
IOB Flip Flops |
410 |
|
|
|
IOB Master Pads |
5 |
|
|
|
IOB Slave Pads |
5 |
|
|
|
Number of bonded IPADs |
4 |
32 |
12% |
|
Number of LOCed IPADs |
4 |
4 |
100% |
|
Number of bonded OPADs |
16 |
16 |
100% |
|
Number of LOCed OPADs |
16 |
16 |
100% |
|
Number of RAMB16BWERs |
1 |
268 |
1% |
|
Number of RAMB8BWERs |
43 |
536 |
8% |
|
Number of BUFIO2/BUFIO2_2CLKs |
3 |
32 |
9% |
|
Number used as BUFIO2s |
3 |
|
|
|
Number used as BUFIO2_2CLKs |
0 |
|
|
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
3 |
32 |
9% |
|
Number used as BUFIO2FBs |
3 |
|
|
|
Number used as BUFIO2FB_2CLKs |
0 |
|
|
|
Number of BUFG/BUFGMUXs |
12 |
16 |
75% |
|
Number used as BUFGs |
12 |
|
|
|
Number used as BUFGMUX |
0 |
|
|
|
Number of DCM/DCM_CLKGENs |
3 |
12 |
25% |
|
Number used as DCMs |
3 |
|
|
|
Number used as DCM_CLKGENs |
0 |
|
|
|
Number of ILOGIC2/ISERDES2s |
338 |
586 |
57% |
|
Number used as ILOGIC2s |
338 |
|
|
|
Number used as ISERDES2s |
0 |
|
|
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
586 |
0% |
|
Number of OLOGIC2/OSERDES2s |
71 |
586 |
12% |
|
Number used as OLOGIC2s |
71 |
|
|
|
Number used as OSERDES2s |
0 |
|
|
|
Number of BSCANs |
2 |
4 |
50% |
|
Number of BUFHs |
0 |
384 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
Number of DSP48A1s |
0 |
180 |
0% |
|
Number of GTPA1_DUALs |
4 |
4 |
100% |
|
Number of ICAPs |
0 |
1 |
0% |
|
Number of MCBs |
0 |
4 |
0% |
|
Number of PCIE_A1s |
0 |
1 |
0% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
0 |
6 |
0% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Average Fanout of Non-Clock Nets |
3.06 |
|
|
|