Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (ISE) - P.20131013 Target Family: Spartan6
OS Platform: NT Target Device: xc6slx150t
Project ID (random number) de5ff6bd725140149f3281452ebea94c.5791F61FD98743B7987AE3F307838D55.14 Target Package: fgg900
Registration ID 179841159_203016066_210686459_760 Target Speed: -3
Date Generated 2022-06-17T09:56:32 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4590 CPU @ 3.30GHz CPU Speed 3292 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4590 CPU @ 3.30GHz CPU Speed 3292 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=161
  • 1-bit comparator equal=8
  • 5-bit comparator greater=153
Counters=38
  • 12-bit up counter=1
  • 16-bit up counter=21
  • 19-bit up counter=1
  • 22-bit up counter=7
  • 6-bit up counter=8
Multiplexers=545
  • 1-bit 2-to-1 multiplexer=376
  • 16-bit 2-to-1 multiplexer=6
  • 32-bit 2-to-1 multiplexer=72
  • 4-bit 2-to-1 multiplexer=39
  • 64-bit 2-to-1 multiplexer=4
  • 7-bit 2-to-1 multiplexer=18
  • 76-bit 2-to-1 multiplexer=8
  • 8-bit 2-to-1 multiplexer=18
  • 9-bit 2-to-1 multiplexer=4
RAMs=4
  • 64x64-bit single-port distributed Read Only RAM=4
Registers=4590
  • Flip-Flops=4590
Xors=624
  • 1-bit xor2=608
  • 1-bit xor35=2
  • 1-bit xor37=14
MiscellaneousStatistics
  • AGG_BONDED_IO=509
  • AGG_IO=509
  • AGG_LOCED_IO=509
  • AGG_SLICE=4168
  • NUM_BONDED_IOB=499
  • NUM_BONDED_IOBM=5
  • NUM_BONDED_IOBS=5
  • NUM_BONDED_IPAD=4
  • NUM_BONDED_OPAD=16
  • NUM_BSCAN=2
  • NUM_BSFULL=5916
  • NUM_BSLUTONLY=3502
  • NUM_BSREGONLY=2804
  • NUM_BSUSED=12222
  • NUM_BUFDS=2
  • NUM_BUFG=12
  • NUM_BUFIO2=3
  • NUM_BUFIO2FB=3
  • NUM_DCM=3
  • NUM_GTPA1_DUAL=4
  • NUM_ILOGIC2=338
  • NUM_IOB_FF=410
  • NUM_LOCED_IOB=499
  • NUM_LOCED_IOBM=5
  • NUM_LOCED_IOBS=5
  • NUM_LOCED_IPAD=4
  • NUM_LOCED_OPAD=16
  • NUM_LOGIC_O5ANDO6=1746
  • NUM_LOGIC_O5ONLY=452
  • NUM_LOGIC_O6ONLY=6265
  • NUM_LUT_RT_DRIVES_CARRY4=38
  • NUM_LUT_RT_DRIVES_FLOP=860
  • NUM_LUT_RT_EXO5=860
  • NUM_LUT_RT_EXO6=38
  • NUM_LUT_RT_O5=475
  • NUM_LUT_RT_O6=452
  • NUM_OLOGIC2=71
  • NUM_RAMB16BWER=1
  • NUM_RAMB8BWER=43
  • NUM_SLICEL=565
  • NUM_SLICEM=20
  • NUM_SLICEX=3583
  • NUM_SLICE_CARRY4=566
  • NUM_SLICE_CONTROLSET=595
  • NUM_SLICE_CYINIT=12326
  • NUM_SLICE_F7MUX=12
  • NUM_SLICE_F8MUX=2
  • NUM_SLICE_FF=10582
  • NUM_SLICE_LATCH=11
  • NUM_SLICE_UNUSEDCTRL=949
  • NUM_SRL_O5ANDO6=9
  • NUM_SRL_O6ONLY=48
  • NUM_UNUSABLE_FF_BELS=3277
  • Xilinx Core chipscope_icon_v1_06_a, Xilinx CORE Generator 14.7=2
  • Xilinx Core chipscope_ila_v1_05_a, Xilinx CORE Generator 14.7=1
  • Xilinx Core chipscope_vio_v1_05_a, Xilinx CORE Generator 14.7=1
  • Xilinx Core fifo_generator_v6_2, Xilinx CORE Generator 12.3=42
NetStatistics
  • NumNets_Active=17220
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=464
  • NumNodesOfType_Active_BOUNCEIN=2211
  • NumNodesOfType_Active_BUFGOUT=12
  • NumNodesOfType_Active_BUFHINP2OUT=65
  • NumNodesOfType_Active_BUFIOINP=6
  • NumNodesOfType_Active_CLKPIN=3335
  • NumNodesOfType_Active_CLKPINFEED=153
  • NumNodesOfType_Active_CNTRLPIN=2657
  • NumNodesOfType_Active_DOUBLE=28542
  • NumNodesOfType_Active_GENERIC=961
  • NumNodesOfType_Active_GLOBAL=1274
  • NumNodesOfType_Active_INPUT=2223
  • NumNodesOfType_Active_IOBIN2OUT=862
  • NumNodesOfType_Active_IOBOUTPUT=550
  • NumNodesOfType_Active_LUTINPUT=35412
  • NumNodesOfType_Active_OUTBOUND=16908
  • NumNodesOfType_Active_OUTPUT=16332
  • NumNodesOfType_Active_PADINPUT=136
  • NumNodesOfType_Active_PADOUTPUT=408
  • NumNodesOfType_Active_PINBOUNCE=9880
  • NumNodesOfType_Active_PINFEED=43017
  • NumNodesOfType_Active_PINFEED1=9
  • NumNodesOfType_Active_PINFEED2=421
  • NumNodesOfType_Active_QUAD=43264
  • NumNodesOfType_Active_REGINPUT=4188
  • NumNodesOfType_Active_SINGLE=29669
  • NumNodesOfType_Gnd_BOUNCEACROSS=14
  • NumNodesOfType_Gnd_BOUNCEIN=683
  • NumNodesOfType_Gnd_CLKPIN=15
  • NumNodesOfType_Gnd_CNTRLPIN=18
  • NumNodesOfType_Gnd_DOUBLE=27
  • NumNodesOfType_Gnd_GENERIC=4
  • NumNodesOfType_Gnd_HGNDOUT=401
  • NumNodesOfType_Gnd_INPUT=2484
  • NumNodesOfType_Gnd_IOBIN2OUT=13
  • NumNodesOfType_Gnd_IOBOUTPUT=4
  • NumNodesOfType_Gnd_LUTINPUT=15
  • NumNodesOfType_Gnd_OUTBOUND=61
  • NumNodesOfType_Gnd_OUTPUT=88
  • NumNodesOfType_Gnd_PADINPUT=4
  • NumNodesOfType_Gnd_PINBOUNCE=1149
  • NumNodesOfType_Gnd_PINFEED=2251
  • NumNodesOfType_Gnd_REGINPUT=314
  • NumNodesOfType_Gnd_SINGLE=51
  • NumNodesOfType_Vcc_CNTRLPIN=13
  • NumNodesOfType_Vcc_HVCCOUT=935
  • NumNodesOfType_Vcc_INPUT=213
  • NumNodesOfType_Vcc_IOBINPUT=9
  • NumNodesOfType_Vcc_KVCCOUT=112
  • NumNodesOfType_Vcc_LUTINPUT=2837
  • NumNodesOfType_Vcc_PINBOUNCE=70
  • NumNodesOfType_Vcc_PINFEED=3040
  • NumNodesOfType_Vcc_REGINPUT=38
SiteStatistics
  • BUFG-BUFGMUX=12
  • IOB-IOBM=249
  • IOB-IOBS=250
  • SLICEL-SLICEM=241
  • SLICEX-SLICEL=845
  • SLICEX-SLICEM=740
SiteSummary
  • BSCAN=2
  • BSCAN_BSCAN=2
  • BUFDS=2
  • BUFDS_BUFDS=2
  • BUFG=12
  • BUFG_BUFG=12
  • BUFIO2=3
  • BUFIO2FB=3
  • BUFIO2FB_BUFIO2FB=3
  • BUFIO2_BUFIO2=3
  • CARRY4=566
  • DCM=3
  • DCM_DCM=3
  • FF_SR=1890
  • GTPA1_DUAL=4
  • GTPA1_DUAL_GTPA1_DUAL=4
  • HARD0=367
  • HARD1=197
  • ILOGIC2=338
  • ILOGIC2_IFF=338
  • INVERTER=21
  • IOB=499
  • IOBM=5
  • IOBM_OUTBUF=5
  • IOBS=5
  • IOB_IMUX=406
  • IOB_INBUF=406
  • IOB_OUTBUF=109
  • IPAD=4
  • IPAD_IPAD=4
  • IPAD_PAD=4
  • LUT5=3533
  • LUT6=8500
  • LUT_OR_MEM5=9
  • LUT_OR_MEM6=58
  • NULLMUX=7
  • OLOGIC2=71
  • OLOGIC2_OUTFF=71
  • OLOGIC2_T1USED=1
  • OLOGIC2_TFF=1
  • OPAD=16
  • OPAD_OPAD=16
  • OPAD_PAD=16
  • PAD=509
  • PULL_OR_KEEP1=304
  • RAMB16BWER=1
  • RAMB16BWER_RAMB16BWER=1
  • RAMB8BWER=43
  • RAMB8BWER_RAMB8BWER=43
  • REG_SR=8703
  • SELMUX2_1=369
  • SLICEL=565
  • SLICEM=20
  • SLICEX=3583
 
Configuration Data
BSCAN_BSCAN
  • JTAG_CHAIN=[1:2]
  • JTAG_TEST=[0:2]
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:3]
  • INVERT_INPUTS=[FALSE:3]
BUFIO2_BUFIO2
  • DIVIDE=[1:3]
  • DIVIDE_BYPASS=[TRUE:3]
  • I_INVERT=[FALSE:3]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:3]
  • PSEN=[PSEN_INV:0] [PSEN:3]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:3]
  • RST=[RST:3] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2.0:3]
  • CLKIN_DIVIDE_BY_2=[FALSE:3]
  • CLKOUT_PHASE_SHIFT=[NONE:3]
  • CLK_FEEDBACK=[1X:3]
  • DESKEW_ADJUST=[5:3]
  • DFS_FREQUENCY_MODE=[LOW:3]
  • DLL_FREQUENCY_MODE=[LOW:3]
  • DSS_MODE=[NONE:3]
  • DUTY_CYCLE_CORRECTION=[TRUE:3]
  • PSCLK=[PSCLK_INV:0] [PSCLK:3]
  • PSEN=[PSEN_INV:0] [PSEN:3]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:3]
  • RST=[RST:3] [RST_INV:0]
  • STARTUP_WAIT=[TRUE:3]
  • VERY_HIGH_FREQUENCY=[FALSE:3]
FF_SR
  • CK=[CK:1882] [CK_INV:8]
  • SRINIT=[SRINIT0:1716] [SRINIT1:174]
  • SYNC_ATTR=[ASYNC:1586] [SYNC:304]
GTPA1_DUAL
  • DCLK=[DCLK_INV:0] [DCLK:4]
  • RXUSRCLK0=[RXUSRCLK0:4] [RXUSRCLK0_INV:0]
  • RXUSRCLK1=[RXUSRCLK1:4] [RXUSRCLK1_INV:0]
  • RXUSRCLK20=[RXUSRCLK20:4] [RXUSRCLK20_INV:0]
  • RXUSRCLK21=[RXUSRCLK21:4] [RXUSRCLK21_INV:0]
  • TSTCLK0=[TSTCLK0:4] [TSTCLK0_INV:0]
  • TSTCLK1=[TSTCLK1_INV:0] [TSTCLK1:4]
  • TXUSRCLK0=[TXUSRCLK0:4] [TXUSRCLK0_INV:0]
  • TXUSRCLK1=[TXUSRCLK1:4] [TXUSRCLK1_INV:0]
  • TXUSRCLK20=[TXUSRCLK20_INV:0] [TXUSRCLK20:4]
  • TXUSRCLK21=[TXUSRCLK21_INV:0] [TXUSRCLK21:4]
GTPA1_DUAL_GTPA1_DUAL
  • AC_CAP_DIS_0=[FALSE:4]
  • AC_CAP_DIS_1=[FALSE:4]
  • ALIGN_COMMA_WORD_0=[1:4]
  • ALIGN_COMMA_WORD_1=[1:4]
  • CB2_INH_CC_PERIOD_0=[8:4]
  • CB2_INH_CC_PERIOD_1=[8:4]
  • CHAN_BOND_1_MAX_SKEW_0=[1:4]
  • CHAN_BOND_1_MAX_SKEW_1=[1:4]
  • CHAN_BOND_2_MAX_SKEW_0=[1:4]
  • CHAN_BOND_2_MAX_SKEW_1=[1:4]
  • CHAN_BOND_KEEP_ALIGN_0=[FALSE:4]
  • CHAN_BOND_KEEP_ALIGN_1=[FALSE:4]
  • CHAN_BOND_SEQ_2_USE_0=[FALSE:4]
  • CHAN_BOND_SEQ_2_USE_1=[FALSE:4]
  • CHAN_BOND_SEQ_LEN_0=[1:4]
  • CHAN_BOND_SEQ_LEN_1=[1:4]
  • CLK25_DIVIDER_0=[10:4]
  • CLK25_DIVIDER_1=[10:4]
  • CLKINDC_B_0=[TRUE:4]
  • CLKINDC_B_1=[TRUE:4]
  • CLKRCV_TRST_0=[TRUE:4]
  • CLKRCV_TRST_1=[TRUE:4]
  • CLK_CORRECT_USE_0=[FALSE:4]
  • CLK_CORRECT_USE_1=[FALSE:4]
  • CLK_COR_ADJ_LEN_0=[1:4]
  • CLK_COR_ADJ_LEN_1=[1:4]
  • CLK_COR_DET_LEN_0=[1:4]
  • CLK_COR_DET_LEN_1=[1:4]
  • CLK_COR_INSERT_IDLE_FLAG_0=[FALSE:4]
  • CLK_COR_INSERT_IDLE_FLAG_1=[FALSE:4]
  • CLK_COR_KEEP_IDLE_0=[FALSE:4]
  • CLK_COR_KEEP_IDLE_1=[FALSE:4]
  • CLK_COR_MAX_LAT_0=[18:4]
  • CLK_COR_MAX_LAT_1=[18:4]
  • CLK_COR_MIN_LAT_0=[16:4]
  • CLK_COR_MIN_LAT_1=[16:4]
  • CLK_COR_PRECEDENCE_0=[TRUE:4]
  • CLK_COR_PRECEDENCE_1=[TRUE:4]
  • CLK_COR_REPEAT_WAIT_0=[5:4]
  • CLK_COR_REPEAT_WAIT_1=[5:4]
  • CLK_COR_SEQ_2_USE_0=[FALSE:4]
  • CLK_COR_SEQ_2_USE_1=[FALSE:4]
  • CLK_OUT_GTP_SEL_0=[REFCLKPLL0:4]
  • CLK_OUT_GTP_SEL_1=[REFCLKPLL1:4]
  • DCLK=[DCLK_INV:0] [DCLK:4]
  • DEC_MCOMMA_DETECT_0=[FALSE:4]
  • DEC_MCOMMA_DETECT_1=[FALSE:4]
  • DEC_PCOMMA_DETECT_0=[FALSE:4]
  • DEC_PCOMMA_DETECT_1=[FALSE:4]
  • DEC_VALID_COMMA_ONLY_0=[FALSE:4]
  • DEC_VALID_COMMA_ONLY_1=[FALSE:4]
  • GTP_CFG_PWRUP_0=[TRUE:4]
  • GTP_CFG_PWRUP_1=[TRUE:4]
  • LOOPBACK_DRP_EN_0=[FALSE:4]
  • LOOPBACK_DRP_EN_1=[FALSE:4]
  • MASTER_DRP_EN_0=[FALSE:4]
  • MASTER_DRP_EN_1=[FALSE:4]
  • MCOMMA_DETECT_0=[TRUE:4]
  • MCOMMA_DETECT_1=[TRUE:4]
  • OOB_CLK_DIVIDER_0=[6:4]
  • OOB_CLK_DIVIDER_1=[6:4]
  • PCI_EXPRESS_MODE_0=[FALSE:4]
  • PCI_EXPRESS_MODE_1=[FALSE:4]
  • PCOMMA_DETECT_0=[TRUE:4]
  • PCOMMA_DETECT_1=[TRUE:4]
  • PDELIDLE_DRP_EN_0=[FALSE:4]
  • PDELIDLE_DRP_EN_1=[FALSE:4]
  • PHASEALIGN_DRP_EN_0=[FALSE:4]
  • PHASEALIGN_DRP_EN_1=[FALSE:4]
  • PLL_DIVSEL_FB_0=[2:4]
  • PLL_DIVSEL_FB_1=[2:4]
  • PLL_DIVSEL_REF_0=[1:4]
  • PLL_DIVSEL_REF_1=[1:4]
  • PLL_DRP_EN_0=[FALSE:4]
  • PLL_DRP_EN_1=[FALSE:4]
  • PLL_RXDIVSEL_OUT_0=[1:4]
  • PLL_RXDIVSEL_OUT_1=[1:4]
  • PLL_SATA_0=[FALSE:4]
  • PLL_SATA_1=[FALSE:4]
  • PLL_SOURCE_0=[PLL0:4]
  • PLL_SOURCE_1=[PLL1:4]
  • PLL_STARTUP_EN_0=[TRUE:4]
  • PLL_STARTUP_EN_1=[TRUE:4]
  • PLL_TXDIVSEL_OUT_0=[1:4]
  • PLL_TXDIVSEL_OUT_1=[1:4]
  • POLARITY_DRP_EN_0=[FALSE:4]
  • POLARITY_DRP_EN_1=[FALSE:4]
  • PRBS_DRP_EN_0=[FALSE:4]
  • PRBS_DRP_EN_1=[FALSE:4]
  • RCV_TERM_GND_0=[FALSE:4]
  • RCV_TERM_GND_1=[FALSE:4]
  • RCV_TERM_VTTRX_0=[TRUE:4]
  • RCV_TERM_VTTRX_1=[TRUE:4]
  • RESET_DRP_EN_0=[FALSE:4]
  • RESET_DRP_EN_1=[FALSE:4]
  • RXEQ_DRP_EN_0=[FALSE:4]
  • RXEQ_DRP_EN_1=[FALSE:4]
  • RXUSRCLK0=[RXUSRCLK0:4] [RXUSRCLK0_INV:0]
  • RXUSRCLK1=[RXUSRCLK1:4] [RXUSRCLK1_INV:0]
  • RXUSRCLK20=[RXUSRCLK20:4] [RXUSRCLK20_INV:0]
  • RXUSRCLK21=[RXUSRCLK21:4] [RXUSRCLK21_INV:0]
  • RX_BUFFER_USE_0=[TRUE:4]
  • RX_BUFFER_USE_1=[TRUE:4]
  • RX_CDR_FORCE_ROTATE_0=[FALSE:4]
  • RX_CDR_FORCE_ROTATE_1=[FALSE:4]
  • RX_DECODE_SEQ_MATCH_0=[TRUE:4]
  • RX_DECODE_SEQ_MATCH_1=[TRUE:4]
  • RX_EN_IDLE_HOLD_CDR_0=[FALSE:4]
  • RX_EN_IDLE_HOLD_CDR_1=[FALSE:4]
  • RX_EN_IDLE_RESET_BUF_0=[FALSE:4]
  • RX_EN_IDLE_RESET_BUF_1=[FALSE:4]
  • RX_EN_IDLE_RESET_FR_0=[FALSE:4]
  • RX_EN_IDLE_RESET_FR_1=[FALSE:4]
  • RX_EN_IDLE_RESET_PH_0=[FALSE:4]
  • RX_EN_IDLE_RESET_PH_1=[FALSE:4]
  • RX_EN_MODE_RESET_BUF_0=[FALSE:4]
  • RX_EN_MODE_RESET_BUF_1=[FALSE:4]
  • RX_LOSS_OF_SYNC_FSM_0=[FALSE:4]
  • RX_LOSS_OF_SYNC_FSM_1=[FALSE:4]
  • RX_LOS_INVALID_INCR_0=[8:4]
  • RX_LOS_INVALID_INCR_1=[8:4]
  • RX_LOS_THRESHOLD_0=[128:4]
  • RX_LOS_THRESHOLD_1=[128:4]
  • RX_SLIDE_MODE_0=[PCS:4]
  • RX_SLIDE_MODE_1=[PCS:4]
  • RX_STATUS_FMT_0=[PCIE:4]
  • RX_STATUS_FMT_1=[PCIE:4]
  • RX_XCLK_SEL_0=[RXREC:4]
  • RX_XCLK_SEL_1=[RXREC:4]
  • SATA_MAX_BURST_0=[8:4]
  • SATA_MAX_BURST_1=[8:4]
  • SATA_MAX_INIT_0=[23:4]
  • SATA_MAX_INIT_1=[23:4]
  • SATA_MAX_WAKE_0=[8:4]
  • SATA_MAX_WAKE_1=[8:4]
  • SATA_MIN_BURST_0=[4:4]
  • SATA_MIN_BURST_1=[4:4]
  • SATA_MIN_INIT_0=[13:4]
  • SATA_MIN_INIT_1=[13:4]
  • SATA_MIN_WAKE_0=[4:4]
  • SATA_MIN_WAKE_1=[4:4]
  • TERMINATION_OVRD_0=[FALSE:4]
  • TERMINATION_OVRD_1=[FALSE:4]
  • TSTCLK0=[TSTCLK0:4] [TSTCLK0_INV:0]
  • TSTCLK1=[TSTCLK1_INV:0] [TSTCLK1:4]
  • TXDRIVE_DRP_EN_0=[FALSE:4]
  • TXDRIVE_DRP_EN_1=[FALSE:4]
  • TXUSRCLK0=[TXUSRCLK0:4] [TXUSRCLK0_INV:0]
  • TXUSRCLK1=[TXUSRCLK1:4] [TXUSRCLK1_INV:0]
  • TXUSRCLK20=[TXUSRCLK20_INV:0] [TXUSRCLK20:4]
  • TXUSRCLK21=[TXUSRCLK21_INV:0] [TXUSRCLK21:4]
  • TX_BUFFER_USE_0=[TRUE:4]
  • TX_BUFFER_USE_1=[TRUE:4]
  • TX_XCLK_SEL_0=[TXOUT:4]
  • TX_XCLK_SEL_1=[TXOUT:4]
ILOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:338]
ILOGIC2_IFF
  • CLK0=[CLK0_INV:0] [CLK0:338]
  • IFFTYPE=[FF:338]
  • SRINIT_Q=[0:338]
  • SRTYPE_Q=[ASYNC:1]
IOBM_OUTBUF
  • SUSPEND=[3STATE:5]
IOB_INBUF
  • DIFF_TERM=[TRUE:2]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:109]
  • SLEW=[SLOW:109]
  • SUSPEND=[3STATE:109]
LUT_OR_MEM5
  • CLK=[CLK:9] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:9]
  • RAMMODE=[SRL16:9]
LUT_OR_MEM6
  • CLK=[CLK:57] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:1] [RAM:57]
  • RAMMODE=[SRL16:22] [SRL32:35]
OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:71]
  • CLK1=[CLK1:9] [CLK1_INV:0]
OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:71]
  • CK1=[CK1_INV:0] [CK1:9]
  • DDR_ALIGNMENT=[NONE:9]
  • OUTFFTYPE=[FF:62] [DDR:9]
  • SRINIT_OQ=[0:71]
  • SRTYPE_OQ=[ASYNC:1] [SYNC:9]
OLOGIC2_TFF
  • CK0=[CK0_INV:0] [CK0:1]
  • SRINIT_TQ=[0:1]
  • TFFTYPE=[FF:1]
PULL_OR_KEEP1
  • PULLTYPE=[PULLUP:304]
RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEB=[REGCEB_INV:0] [REGCEB:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:1] [WEB0_INV:0]
  • WEB1=[WEB1:1] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:1]
  • WEB3=[WEB3:1] [WEB3_INV:0]
RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • DATA_WIDTH_A=[18:1]
  • DATA_WIDTH_B=[18:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • EN_RSTRAM_A=[FALSE:1]
  • EN_RSTRAM_B=[FALSE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEB=[REGCEB_INV:0] [REGCEB:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:1] [WEB0_INV:0]
  • WEB1=[WEB1:1] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:1]
  • WEB3=[WEB3:1] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:43] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:43]
  • ENAWREN=[ENAWREN:43] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:43]
  • REGCEA=[REGCEA_INV:0] [REGCEA:43]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:43]
  • RSTA=[RSTA:43] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:43] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:43] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:43]
  • WEBWEU0=[WEBWEU0:43] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:43] [WEBWEU1_INV:0]
RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:43] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:43]
  • DATA_WIDTH_A=[9:1] [18:42]
  • DATA_WIDTH_B=[9:1] [18:42]
  • DOA_REG=[0:43]
  • DOB_REG=[0:43]
  • ENAWREN=[ENAWREN:43] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:43]
  • EN_RSTRAM_A=[FALSE:1] [TRUE:42]
  • EN_RSTRAM_B=[FALSE:1] [TRUE:42]
  • RAM_MODE=[TDP:43]
  • REGCEA=[REGCEA_INV:0] [REGCEA:43]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:43]
  • RSTA=[RSTA:43] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:43] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:43]
  • RST_PRIORITY_A=[CE:43]
  • RST_PRIORITY_B=[CE:43]
  • WEAWEL0=[WEAWEL0:43] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:43]
  • WEBWEU0=[WEBWEU0:43] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:43] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:43]
  • WRITE_MODE_B=[WRITE_FIRST:43]
REG_SR
  • CK=[CK:8110] [CK_INV:593]
  • LATCH_OR_FF=[FF:8692] [LATCH:11]
  • SRINIT=[SRINIT0:7746] [SRINIT1:957]
  • SYNC_ATTR=[ASYNC:8025] [SYNC:678]
SLICEL
  • CLK=[CLK:251] [CLK_INV:3]
SLICEM
  • CLK=[CLK:20] [CLK_INV:0]
SLICEX
  • CLK=[CLK:2777] [CLK_INV:168]
 
Pin Data
BSCAN
  • DRCK=2
  • SEL=2
  • SHIFT=2
  • TDI=2
  • TDO=2
  • UPDATE=2
BSCAN_BSCAN
  • DRCK=2
  • SEL=2
  • SHIFT=2
  • TDI=2
  • TDO=2
  • UPDATE=2
BUFDS
  • I=2
  • IB=2
  • O=2
BUFDS_BUFDS
  • I=2
  • IB=2
  • O=2
BUFG
  • I0=12
  • O=12
BUFG_BUFG
  • I0=12
  • O=12
BUFIO2
  • DIVCLK=3
  • I=3
BUFIO2FB
  • I=3
  • O=3
BUFIO2FB_BUFIO2FB
  • I=3
  • O=3
BUFIO2_BUFIO2
  • DIVCLK=3
  • I=3
CARRY4
  • CIN=340
  • CO0=172
  • CO3=356
  • CYINIT=226
  • DI0=558
  • DI1=376
  • DI2=375
  • DI3=356
  • O0=140
  • O1=136
  • O2=122
  • O3=121
  • S0=566
  • S1=390
  • S2=376
  • S3=375
DCM
  • CLK0=3
  • CLK180=3
  • CLK2X=1
  • CLK2X180=1
  • CLKFB=3
  • CLKFX=1
  • CLKFX180=1
  • CLKIN=3
  • LOCKED=1
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
DCM_DCM
  • CLK0=3
  • CLK180=3
  • CLK2X=1
  • CLK2X180=1
  • CLKFB=3
  • CLKFX=1
  • CLKFX180=1
  • CLKIN=3
  • LOCKED=1
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
FF_SR
  • CE=531
  • CK=1890
  • D=1890
  • Q=1890
  • SR=1464
GTPA1_DUAL
  • CLK00=4
  • CLK01=4
  • DADDR0=4
  • DADDR1=4
  • DADDR2=4
  • DADDR3=4
  • DADDR4=4
  • DADDR5=4
  • DADDR6=4
  • DADDR7=4
  • DCLK=4
  • DEN=4
  • DI0=4
  • DI1=4
  • DI10=4
  • DI11=4
  • DI12=4
  • DI13=4
  • DI14=4
  • DI15=4
  • DI2=4
  • DI3=4
  • DI4=4
  • DI5=4
  • DI6=4
  • DI7=4
  • DI8=4
  • DI9=4
  • DWE=4
  • GATERXELECIDLE0=4
  • GATERXELECIDLE1=4
  • GTPCLKFBSEL0EAST0=4
  • GTPCLKFBSEL0EAST1=4
  • GTPCLKFBSEL0WEST0=4
  • GTPCLKFBSEL0WEST1=4
  • GTPCLKFBSEL1EAST0=4
  • GTPCLKFBSEL1EAST1=4
  • GTPCLKFBSEL1WEST0=4
  • GTPCLKFBSEL1WEST1=4
  • GTPRESET0=4
  • GTPRESET1=4
  • GTPTEST00=4
  • GTPTEST01=4
  • GTPTEST02=4
  • GTPTEST03=4
  • GTPTEST04=4
  • GTPTEST05=4
  • GTPTEST06=4
  • GTPTEST07=4
  • GTPTEST10=4
  • GTPTEST11=4
  • GTPTEST12=4
  • GTPTEST13=4
  • GTPTEST14=4
  • GTPTEST15=4
  • GTPTEST16=4
  • GTPTEST17=4
  • IGNORESIGDET0=4
  • IGNORESIGDET1=4
  • INTDATAWIDTH0=4
  • INTDATAWIDTH1=4
  • LOOPBACK00=4
  • LOOPBACK01=4
  • LOOPBACK02=4
  • LOOPBACK10=4
  • LOOPBACK11=4
  • LOOPBACK12=4
  • PLLLKDET0=4
  • PLLLKDET1=4
  • PLLLKDETEN0=4
  • PLLLKDETEN1=4
  • PLLPOWERDOWN0=4
  • PLLPOWERDOWN1=4
  • PRBSCNTRESET0=4
  • PRBSCNTRESET1=4
  • REFCLKPWRDNB0=4
  • REFCLKPWRDNB1=4
  • REFSELDYPLL00=4
  • REFSELDYPLL01=4
  • REFSELDYPLL02=4
  • REFSELDYPLL10=4
  • REFSELDYPLL11=4
  • REFSELDYPLL12=4
  • RESETDONE0=4
  • RESETDONE1=4
  • RXBUFRESET0=4
  • RXBUFRESET1=4
  • RXCDRRESET0=4
  • RXCDRRESET1=4
  • RXCHBONDMASTER0=4
  • RXCHBONDMASTER1=4
  • RXCHBONDSLAVE0=4
  • RXCHBONDSLAVE1=4
  • RXCOMMADETUSE0=4
  • RXCOMMADETUSE1=4
  • RXDATAWIDTH00=4
  • RXDATAWIDTH01=4
  • RXDATAWIDTH10=4
  • RXDATAWIDTH11=4
  • RXDEC8B10BUSE0=4
  • RXDEC8B10BUSE1=4
  • RXENCHANSYNC0=4
  • RXENCHANSYNC1=4
  • RXENMCOMMAALIGN0=4
  • RXENMCOMMAALIGN1=4
  • RXENPCOMMAALIGN0=4
  • RXENPCOMMAALIGN1=4
  • RXENPMAPHASEALIGN0=4
  • RXENPMAPHASEALIGN1=4
  • RXENPRBSTST00=4
  • RXENPRBSTST01=4
  • RXENPRBSTST02=4
  • RXENPRBSTST10=4
  • RXENPRBSTST11=4
  • RXENPRBSTST12=4
  • RXEQMIX00=4
  • RXEQMIX01=4
  • RXEQMIX10=4
  • RXEQMIX11=4
  • RXPMASETPHASE0=4
  • RXPMASETPHASE1=4
  • RXPOLARITY0=4
  • RXPOLARITY1=4
  • RXPOWERDOWN00=4
  • RXPOWERDOWN01=4
  • RXPOWERDOWN10=4
  • RXPOWERDOWN11=4
  • RXRESET0=4
  • RXRESET1=4
  • RXSLIDE0=4
  • RXSLIDE1=4
  • RXUSRCLK0=4
  • RXUSRCLK1=4
  • RXUSRCLK20=4
  • RXUSRCLK21=4
  • TSTCLK0=4
  • TSTCLK1=4
  • TSTIN00=4
  • TSTIN01=4
  • TSTIN010=4
  • TSTIN011=4
  • TSTIN02=4
  • TSTIN03=4
  • TSTIN04=4
  • TSTIN05=4
  • TSTIN06=4
  • TSTIN07=4
  • TSTIN08=4
  • TSTIN09=4
  • TSTIN10=4
  • TSTIN11=4
  • TSTIN110=4
  • TSTIN111=4
  • TSTIN12=4
  • TSTIN13=4
  • TSTIN14=4
  • TSTIN15=4
  • TSTIN16=4
  • TSTIN17=4
  • TSTIN18=4
  • TSTIN19=4
  • TXBUFDIFFCTRL00=4
  • TXBUFDIFFCTRL01=4
  • TXBUFDIFFCTRL02=4
  • TXBUFDIFFCTRL10=4
  • TXBUFDIFFCTRL11=4
  • TXBUFDIFFCTRL12=4
  • TXBYPASS8B10B00=4
  • TXBYPASS8B10B01=4
  • TXBYPASS8B10B02=4
  • TXBYPASS8B10B03=4
  • TXBYPASS8B10B10=4
  • TXBYPASS8B10B11=4
  • TXBYPASS8B10B12=4
  • TXBYPASS8B10B13=4
  • TXCHARDISPMODE00=4
  • TXCHARDISPMODE01=4
  • TXCHARDISPMODE02=4
  • TXCHARDISPMODE03=4
  • TXCHARDISPMODE10=4
  • TXCHARDISPMODE11=4
  • TXCHARDISPMODE12=4
  • TXCHARDISPMODE13=4
  • TXCHARDISPVAL00=4
  • TXCHARDISPVAL01=4
  • TXCHARDISPVAL02=4
  • TXCHARDISPVAL03=4
  • TXCHARDISPVAL10=4
  • TXCHARDISPVAL11=4
  • TXCHARDISPVAL12=4
  • TXCHARDISPVAL13=4
  • TXCHARISK00=4
  • TXCHARISK01=4
  • TXCHARISK02=4
  • TXCHARISK03=4
  • TXCHARISK10=4
  • TXCHARISK11=4
  • TXCHARISK12=4
  • TXCHARISK13=4
  • TXCOMSTART0=4
  • TXCOMSTART1=4
  • TXCOMTYPE0=4
  • TXCOMTYPE1=4
  • TXDATA00=4
  • TXDATA01=4
  • TXDATA010=4
  • TXDATA011=4
  • TXDATA012=4
  • TXDATA013=4
  • TXDATA014=4
  • TXDATA015=4
  • TXDATA016=4
  • TXDATA017=4
  • TXDATA018=4
  • TXDATA019=4
  • TXDATA02=4
  • TXDATA020=4
  • TXDATA021=4
  • TXDATA022=4
  • TXDATA023=4
  • TXDATA024=4
  • TXDATA025=4
  • TXDATA026=4
  • TXDATA027=4
  • TXDATA028=4
  • TXDATA029=4
  • TXDATA03=4
  • TXDATA030=4
  • TXDATA031=4
  • TXDATA04=4
  • TXDATA05=4
  • TXDATA06=4
  • TXDATA07=4
  • TXDATA08=4
  • TXDATA09=4
  • TXDATA10=4
  • TXDATA11=4
  • TXDATA110=4
  • TXDATA111=4
  • TXDATA112=4
  • TXDATA113=4
  • TXDATA114=4
  • TXDATA115=4
  • TXDATA116=4
  • TXDATA117=4
  • TXDATA118=4
  • TXDATA119=4
  • TXDATA12=4
  • TXDATA120=4
  • TXDATA121=4
  • TXDATA122=4
  • TXDATA123=4
  • TXDATA124=4
  • TXDATA125=4
  • TXDATA126=4
  • TXDATA127=4
  • TXDATA128=4
  • TXDATA129=4
  • TXDATA13=4
  • TXDATA130=4
  • TXDATA131=4
  • TXDATA14=4
  • TXDATA15=4
  • TXDATA16=4
  • TXDATA17=4
  • TXDATA18=4
  • TXDATA19=4
  • TXDATAWIDTH00=4
  • TXDATAWIDTH01=4
  • TXDATAWIDTH10=4
  • TXDATAWIDTH11=4
  • TXDETECTRX0=4
  • TXDETECTRX1=4
  • TXDIFFCTRL00=4
  • TXDIFFCTRL01=4
  • TXDIFFCTRL02=4
  • TXDIFFCTRL03=4
  • TXDIFFCTRL10=4
  • TXDIFFCTRL11=4
  • TXDIFFCTRL12=4
  • TXDIFFCTRL13=4
  • TXELECIDLE0=4
  • TXELECIDLE1=4
  • TXENC8B10BUSE0=4
  • TXENC8B10BUSE1=4
  • TXENPMAPHASEALIGN0=4
  • TXENPMAPHASEALIGN1=4
  • TXENPRBSTST00=4
  • TXENPRBSTST01=4
  • TXENPRBSTST02=4
  • TXENPRBSTST10=4
  • TXENPRBSTST11=4
  • TXENPRBSTST12=4
  • TXINHIBIT0=4
  • TXINHIBIT1=4
  • TXN0=4
  • TXN1=4
  • TXP0=4
  • TXP1=4
  • TXPDOWNASYNCH0=4
  • TXPDOWNASYNCH1=4
  • TXPMASETPHASE0=4
  • TXPMASETPHASE1=4
  • TXPOLARITY0=4
  • TXPOLARITY1=4
  • TXPOWERDOWN00=4
  • TXPOWERDOWN01=4
  • TXPOWERDOWN10=4
  • TXPOWERDOWN11=4
  • TXPRBSFORCEERR0=4
  • TXPRBSFORCEERR1=4
  • TXPREEMPHASIS00=4
  • TXPREEMPHASIS01=4
  • TXPREEMPHASIS02=4
  • TXPREEMPHASIS10=4
  • TXPREEMPHASIS11=4
  • TXPREEMPHASIS12=4
  • TXRESET0=4
  • TXRESET1=4
  • TXUSRCLK0=4
  • TXUSRCLK1=4
  • TXUSRCLK20=4
  • TXUSRCLK21=4
  • USRCODEERR0=4
  • USRCODEERR1=4
GTPA1_DUAL_GTPA1_DUAL
  • CLK00=4
  • CLK01=4
  • DADDR0=4
  • DADDR1=4
  • DADDR2=4
  • DADDR3=4
  • DADDR4=4
  • DADDR5=4
  • DADDR6=4
  • DADDR7=4
  • DCLK=4
  • DEN=4
  • DI0=4
  • DI1=4
  • DI10=4
  • DI11=4
  • DI12=4
  • DI13=4
  • DI14=4
  • DI15=4
  • DI2=4
  • DI3=4
  • DI4=4
  • DI5=4
  • DI6=4
  • DI7=4
  • DI8=4
  • DI9=4
  • DWE=4
  • GATERXELECIDLE0=4
  • GATERXELECIDLE1=4
  • GTPCLKFBSEL0EAST0=4
  • GTPCLKFBSEL0EAST1=4
  • GTPCLKFBSEL0WEST0=4
  • GTPCLKFBSEL0WEST1=4
  • GTPCLKFBSEL1EAST0=4
  • GTPCLKFBSEL1EAST1=4
  • GTPCLKFBSEL1WEST0=4
  • GTPCLKFBSEL1WEST1=4
  • GTPRESET0=4
  • GTPRESET1=4
  • GTPTEST00=4
  • GTPTEST01=4
  • GTPTEST02=4
  • GTPTEST03=4
  • GTPTEST04=4
  • GTPTEST05=4
  • GTPTEST06=4
  • GTPTEST07=4
  • GTPTEST10=4
  • GTPTEST11=4
  • GTPTEST12=4
  • GTPTEST13=4
  • GTPTEST14=4
  • GTPTEST15=4
  • GTPTEST16=4
  • GTPTEST17=4
  • IGNORESIGDET0=4
  • IGNORESIGDET1=4
  • INTDATAWIDTH0=4
  • INTDATAWIDTH1=4
  • LOOPBACK00=4
  • LOOPBACK01=4
  • LOOPBACK02=4
  • LOOPBACK10=4
  • LOOPBACK11=4
  • LOOPBACK12=4
  • PLLLKDET0=4
  • PLLLKDET1=4
  • PLLLKDETEN0=4
  • PLLLKDETEN1=4
  • PLLPOWERDOWN0=4
  • PLLPOWERDOWN1=4
  • PRBSCNTRESET0=4
  • PRBSCNTRESET1=4
  • REFCLKPWRDNB0=4
  • REFCLKPWRDNB1=4
  • REFSELDYPLL00=4
  • REFSELDYPLL01=4
  • REFSELDYPLL02=4
  • REFSELDYPLL10=4
  • REFSELDYPLL11=4
  • REFSELDYPLL12=4
  • RESETDONE0=4
  • RESETDONE1=4
  • RXBUFRESET0=4
  • RXBUFRESET1=4
  • RXCDRRESET0=4
  • RXCDRRESET1=4
  • RXCHBONDMASTER0=4
  • RXCHBONDMASTER1=4
  • RXCHBONDSLAVE0=4
  • RXCHBONDSLAVE1=4
  • RXCOMMADETUSE0=4
  • RXCOMMADETUSE1=4
  • RXDATAWIDTH00=4
  • RXDATAWIDTH01=4
  • RXDATAWIDTH10=4
  • RXDATAWIDTH11=4
  • RXDEC8B10BUSE0=4
  • RXDEC8B10BUSE1=4
  • RXENCHANSYNC0=4
  • RXENCHANSYNC1=4
  • RXENMCOMMAALIGN0=4
  • RXENMCOMMAALIGN1=4
  • RXENPCOMMAALIGN0=4
  • RXENPCOMMAALIGN1=4
  • RXENPMAPHASEALIGN0=4
  • RXENPMAPHASEALIGN1=4
  • RXENPRBSTST00=4
  • RXENPRBSTST01=4
  • RXENPRBSTST02=4
  • RXENPRBSTST10=4
  • RXENPRBSTST11=4
  • RXENPRBSTST12=4
  • RXEQMIX00=4
  • RXEQMIX01=4
  • RXEQMIX10=4
  • RXEQMIX11=4
  • RXPMASETPHASE0=4
  • RXPMASETPHASE1=4
  • RXPOLARITY0=4
  • RXPOLARITY1=4
  • RXPOWERDOWN00=4
  • RXPOWERDOWN01=4
  • RXPOWERDOWN10=4
  • RXPOWERDOWN11=4
  • RXRESET0=4
  • RXRESET1=4
  • RXSLIDE0=4
  • RXSLIDE1=4
  • RXUSRCLK0=4
  • RXUSRCLK1=4
  • RXUSRCLK20=4
  • RXUSRCLK21=4
  • TSTCLK0=4
  • TSTCLK1=4
  • TSTIN00=4
  • TSTIN01=4
  • TSTIN010=4
  • TSTIN011=4
  • TSTIN02=4
  • TSTIN03=4
  • TSTIN04=4
  • TSTIN05=4
  • TSTIN06=4
  • TSTIN07=4
  • TSTIN08=4
  • TSTIN09=4
  • TSTIN10=4
  • TSTIN11=4
  • TSTIN110=4
  • TSTIN111=4
  • TSTIN12=4
  • TSTIN13=4
  • TSTIN14=4
  • TSTIN15=4
  • TSTIN16=4
  • TSTIN17=4
  • TSTIN18=4
  • TSTIN19=4
  • TXBUFDIFFCTRL00=4
  • TXBUFDIFFCTRL01=4
  • TXBUFDIFFCTRL02=4
  • TXBUFDIFFCTRL10=4
  • TXBUFDIFFCTRL11=4
  • TXBUFDIFFCTRL12=4
  • TXBYPASS8B10B00=4
  • TXBYPASS8B10B01=4
  • TXBYPASS8B10B02=4
  • TXBYPASS8B10B03=4
  • TXBYPASS8B10B10=4
  • TXBYPASS8B10B11=4
  • TXBYPASS8B10B12=4
  • TXBYPASS8B10B13=4
  • TXCHARDISPMODE00=4
  • TXCHARDISPMODE01=4
  • TXCHARDISPMODE02=4
  • TXCHARDISPMODE03=4
  • TXCHARDISPMODE10=4
  • TXCHARDISPMODE11=4
  • TXCHARDISPMODE12=4
  • TXCHARDISPMODE13=4
  • TXCHARDISPVAL00=4
  • TXCHARDISPVAL01=4
  • TXCHARDISPVAL02=4
  • TXCHARDISPVAL03=4
  • TXCHARDISPVAL10=4
  • TXCHARDISPVAL11=4
  • TXCHARDISPVAL12=4
  • TXCHARDISPVAL13=4
  • TXCHARISK00=4
  • TXCHARISK01=4
  • TXCHARISK02=4
  • TXCHARISK03=4
  • TXCHARISK10=4
  • TXCHARISK11=4
  • TXCHARISK12=4
  • TXCHARISK13=4
  • TXCOMSTART0=4
  • TXCOMSTART1=4
  • TXCOMTYPE0=4
  • TXCOMTYPE1=4
  • TXDATA00=4
  • TXDATA01=4
  • TXDATA010=4
  • TXDATA011=4
  • TXDATA012=4
  • TXDATA013=4
  • TXDATA014=4
  • TXDATA015=4
  • TXDATA016=4
  • TXDATA017=4
  • TXDATA018=4
  • TXDATA019=4
  • TXDATA02=4
  • TXDATA020=4
  • TXDATA021=4
  • TXDATA022=4
  • TXDATA023=4
  • TXDATA024=4
  • TXDATA025=4
  • TXDATA026=4
  • TXDATA027=4
  • TXDATA028=4
  • TXDATA029=4
  • TXDATA03=4
  • TXDATA030=4
  • TXDATA031=4
  • TXDATA04=4
  • TXDATA05=4
  • TXDATA06=4
  • TXDATA07=4
  • TXDATA08=4
  • TXDATA09=4
  • TXDATA10=4
  • TXDATA11=4
  • TXDATA110=4
  • TXDATA111=4
  • TXDATA112=4
  • TXDATA113=4
  • TXDATA114=4
  • TXDATA115=4
  • TXDATA116=4
  • TXDATA117=4
  • TXDATA118=4
  • TXDATA119=4
  • TXDATA12=4
  • TXDATA120=4
  • TXDATA121=4
  • TXDATA122=4
  • TXDATA123=4
  • TXDATA124=4
  • TXDATA125=4
  • TXDATA126=4
  • TXDATA127=4
  • TXDATA128=4
  • TXDATA129=4
  • TXDATA13=4
  • TXDATA130=4
  • TXDATA131=4
  • TXDATA14=4
  • TXDATA15=4
  • TXDATA16=4
  • TXDATA17=4
  • TXDATA18=4
  • TXDATA19=4
  • TXDATAWIDTH00=4
  • TXDATAWIDTH01=4
  • TXDATAWIDTH10=4
  • TXDATAWIDTH11=4
  • TXDETECTRX0=4
  • TXDETECTRX1=4
  • TXDIFFCTRL00=4
  • TXDIFFCTRL01=4
  • TXDIFFCTRL02=4
  • TXDIFFCTRL03=4
  • TXDIFFCTRL10=4
  • TXDIFFCTRL11=4
  • TXDIFFCTRL12=4
  • TXDIFFCTRL13=4
  • TXELECIDLE0=4
  • TXELECIDLE1=4
  • TXENC8B10BUSE0=4
  • TXENC8B10BUSE1=4
  • TXENPMAPHASEALIGN0=4
  • TXENPMAPHASEALIGN1=4
  • TXENPRBSTST00=4
  • TXENPRBSTST01=4
  • TXENPRBSTST02=4
  • TXENPRBSTST10=4
  • TXENPRBSTST11=4
  • TXENPRBSTST12=4
  • TXINHIBIT0=4
  • TXINHIBIT1=4
  • TXN0=4
  • TXN1=4
  • TXP0=4
  • TXP1=4
  • TXPDOWNASYNCH0=4
  • TXPDOWNASYNCH1=4
  • TXPMASETPHASE0=4
  • TXPMASETPHASE1=4
  • TXPOLARITY0=4
  • TXPOLARITY1=4
  • TXPOWERDOWN00=4
  • TXPOWERDOWN01=4
  • TXPOWERDOWN10=4
  • TXPOWERDOWN11=4
  • TXPRBSFORCEERR0=4
  • TXPRBSFORCEERR1=4
  • TXPREEMPHASIS00=4
  • TXPREEMPHASIS01=4
  • TXPREEMPHASIS02=4
  • TXPREEMPHASIS10=4
  • TXPREEMPHASIS11=4
  • TXPREEMPHASIS12=4
  • TXRESET0=4
  • TXRESET1=4
  • TXUSRCLK0=4
  • TXUSRCLK1=4
  • TXUSRCLK20=4
  • TXUSRCLK21=4
  • USRCODEERR0=4
  • USRCODEERR1=4
HARD0
  • 0=367
HARD1
  • 1=197
ILOGIC2
  • CLK0=338
  • D=338
  • FABRICOUT=17
  • Q4=338
  • SR=1
ILOGIC2_IFF
  • CLK0=338
  • D=338
  • Q1=338
  • SR=1
INVERTER
  • IN=21
  • OUT=21
IOB
  • DIFFI_IN=2
  • I=406
  • O=109
  • PAD=499
  • PADOUT=2
  • T=19
IOBM
  • DIFFO_OUT=5
  • O=5
  • PAD=5
IOBM_OUTBUF
  • IN=5
  • OUT=5
  • OUTN=5
IOBS
  • DIFFO_IN=5
  • PAD=5
IOB_IMUX
  • I=385
  • I_B=21
  • OUT=406
IOB_INBUF
  • DIFFI_IN=2
  • OUT=406
  • PAD=406
IOB_OUTBUF
  • IN=109
  • OUT=109
  • TRI=19
IPAD
  • O=4
  • PAD=4
IPAD_IPAD
  • I=4
  • O=4
IPAD_PAD
  • PAD=4
LUT5
  • A1=278
  • A2=409
  • A3=658
  • A4=936
  • A5=724
  • O5=3533
LUT6
  • A1=2526
  • A2=4113
  • A3=5726
  • A4=7740
  • A5=7468
  • A6=8370
  • O6=8500
LUT_OR_MEM5
  • A1=9
  • A2=9
  • A3=9
  • A4=9
  • A5=9
  • CLK=9
  • DI1=9
  • O5=9
  • WE=9
LUT_OR_MEM6
  • A1=58
  • A2=58
  • A3=58
  • A4=58
  • A5=58
  • A6=58
  • CLK=57
  • DI1=35
  • DI2=22
  • MC31=43
  • O6=58
  • WE=57
NULLMUX
  • 0=7
  • OUT=7
OLOGIC2
  • CLK0=71
  • CLK1=9
  • D1=71
  • D2=9
  • OCE=9
  • OQ=71
  • SR=10
  • T1=1
  • TQ=1
OLOGIC2_OUTFF
  • CE=9
  • CK0=71
  • CK1=9
  • D1=71
  • D2=9
  • Q=71
  • SR=10
OLOGIC2_T1USED
  • 0=1
  • OUT=1
OLOGIC2_TFF
  • CK0=1
  • D1=1
  • Q=1
OPAD
  • I=16
  • PAD=16
OPAD_OPAD
  • I=16
  • O=16
OPAD_PAD
  • PAD=16
PAD
  • PAD=509
PULL_OR_KEEP1
  • PAD=304
RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=1
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=1
  • DIA30=1
  • DIA31=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • ENB=1
  • REGCEA=1
  • REGCEB=1
  • RSTA=1
  • RSTB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
RAMB16BWER_RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=1
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=1
  • DIA30=1
  • DIA31=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • ENB=1
  • REGCEA=1
  • REGCEB=1
  • RSTA=1
  • RSTB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
RAMB8BWER
  • ADDRAWRADDR0=43
  • ADDRAWRADDR1=43
  • ADDRAWRADDR10=43
  • ADDRAWRADDR11=43
  • ADDRAWRADDR12=43
  • ADDRAWRADDR2=43
  • ADDRAWRADDR3=43
  • ADDRAWRADDR4=43
  • ADDRAWRADDR5=43
  • ADDRAWRADDR6=43
  • ADDRAWRADDR7=43
  • ADDRAWRADDR8=43
  • ADDRAWRADDR9=43
  • ADDRBRDADDR0=43
  • ADDRBRDADDR1=43
  • ADDRBRDADDR10=43
  • ADDRBRDADDR11=43
  • ADDRBRDADDR12=43
  • ADDRBRDADDR2=43
  • ADDRBRDADDR3=43
  • ADDRBRDADDR4=43
  • ADDRBRDADDR5=43
  • ADDRBRDADDR6=43
  • ADDRBRDADDR7=43
  • ADDRBRDADDR8=43
  • ADDRBRDADDR9=43
  • CLKAWRCLK=43
  • CLKBRDCLK=43
  • DIADI0=43
  • DIADI1=43
  • DIADI10=43
  • DIADI11=43
  • DIADI12=43
  • DIADI13=43
  • DIADI14=43
  • DIADI15=43
  • DIADI2=43
  • DIADI3=43
  • DIADI4=43
  • DIADI5=43
  • DIADI6=43
  • DIADI7=43
  • DIADI8=43
  • DIADI9=43
  • DIBDI0=43
  • DIBDI1=43
  • DIBDI10=43
  • DIBDI11=43
  • DIBDI12=43
  • DIBDI13=43
  • DIBDI14=43
  • DIBDI15=43
  • DIBDI2=43
  • DIBDI3=43
  • DIBDI4=43
  • DIBDI5=43
  • DIBDI6=43
  • DIBDI7=43
  • DIBDI8=43
  • DIBDI9=43
  • DIPADIP0=43
  • DIPADIP1=43
  • DIPBDIP0=43
  • DIPBDIP1=43
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • DOADO4=1
  • DOADO5=1
  • DOADO6=1
  • DOADO7=1
  • DOBDO0=42
  • DOBDO1=42
  • DOBDO10=42
  • DOBDO11=42
  • DOBDO2=42
  • DOBDO3=42
  • DOBDO8=42
  • DOBDO9=42
  • DOPADOP0=1
  • ENAWREN=43
  • ENBRDEN=43
  • REGCEA=43
  • REGCEBREGCE=43
  • RSTA=43
  • RSTBRST=43
  • WEAWEL0=43
  • WEAWEL1=43
  • WEBWEU0=43
  • WEBWEU1=43
RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR0=43
  • ADDRAWRADDR1=43
  • ADDRAWRADDR10=43
  • ADDRAWRADDR11=43
  • ADDRAWRADDR12=43
  • ADDRAWRADDR2=43
  • ADDRAWRADDR3=43
  • ADDRAWRADDR4=43
  • ADDRAWRADDR5=43
  • ADDRAWRADDR6=43
  • ADDRAWRADDR7=43
  • ADDRAWRADDR8=43
  • ADDRAWRADDR9=43
  • ADDRBRDADDR0=43
  • ADDRBRDADDR1=43
  • ADDRBRDADDR10=43
  • ADDRBRDADDR11=43
  • ADDRBRDADDR12=43
  • ADDRBRDADDR2=43
  • ADDRBRDADDR3=43
  • ADDRBRDADDR4=43
  • ADDRBRDADDR5=43
  • ADDRBRDADDR6=43
  • ADDRBRDADDR7=43
  • ADDRBRDADDR8=43
  • ADDRBRDADDR9=43
  • CLKAWRCLK=43
  • CLKBRDCLK=43
  • DIADI0=43
  • DIADI1=43
  • DIADI10=43
  • DIADI11=43
  • DIADI12=43
  • DIADI13=43
  • DIADI14=43
  • DIADI15=43
  • DIADI2=43
  • DIADI3=43
  • DIADI4=43
  • DIADI5=43
  • DIADI6=43
  • DIADI7=43
  • DIADI8=43
  • DIADI9=43
  • DIBDI0=43
  • DIBDI1=43
  • DIBDI10=43
  • DIBDI11=43
  • DIBDI12=43
  • DIBDI13=43
  • DIBDI14=43
  • DIBDI15=43
  • DIBDI2=43
  • DIBDI3=43
  • DIBDI4=43
  • DIBDI5=43
  • DIBDI6=43
  • DIBDI7=43
  • DIBDI8=43
  • DIBDI9=43
  • DIPADIP0=43
  • DIPADIP1=43
  • DIPBDIP0=43
  • DIPBDIP1=43
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • DOADO4=1
  • DOADO5=1
  • DOADO6=1
  • DOADO7=1
  • DOBDO0=42
  • DOBDO1=42
  • DOBDO10=42
  • DOBDO11=42
  • DOBDO2=42
  • DOBDO3=42
  • DOBDO8=42
  • DOBDO9=42
  • DOPADOP0=1
  • ENAWREN=43
  • ENBRDEN=43
  • REGCEA=43
  • REGCEBREGCE=43
  • RSTA=43
  • RSTBRST=43
  • WEAWEL0=43
  • WEAWEL1=43
  • WEBWEU0=43
  • WEBWEU1=43
REG_SR
  • CE=2269
  • CK=8703
  • D=8703
  • Q=8703
  • SR=4783
SELMUX2_1
  • 0=369
  • 1=14
  • OUT=369
  • S0=369
SLICEL
  • A=2
  • A1=81
  • A2=249
  • A3=250
  • A4=558
  • A5=418
  • A6=554
  • AMUX=169
  • AQ=185
  • AX=36
  • B=3
  • B1=52
  • B2=242
  • B3=250
  • B4=387
  • B5=251
  • B6=373
  • BMUX=1
  • BQ=184
  • BX=48
  • C1=77
  • C2=258
  • C3=258
  • C4=381
  • C5=263
  • C6=380
  • CE=162
  • CIN=338
  • CLK=254
  • CMUX=11
  • COUT=334
  • CQ=178
  • CX=55
  • D=18
  • D1=83
  • D2=257
  • D3=260
  • D4=384
  • D5=284
  • D6=376
  • DMUX=29
  • DQ=224
  • DX=98
  • SR=240
SLICEM
  • A=5
  • A1=19
  • A2=19
  • A3=19
  • A4=19
  • A5=19
  • A6=19
  • AI=8
  • AMUX=5
  • AQ=5
  • AX=14
  • B=1
  • B1=14
  • B2=14
  • B3=14
  • B4=14
  • B5=14
  • B6=14
  • BI=3
  • BMUX=4
  • BQ=4
  • BX=12
  • C=2
  • C1=13
  • C2=13
  • C3=13
  • C4=13
  • C5=13
  • C6=13
  • CE=20
  • CI=2
  • CIN=2
  • CLK=20
  • CMUX=3
  • COUT=6
  • CQ=3
  • CX=13
  • D=1
  • D1=12
  • D2=12
  • D3=12
  • D4=12
  • D5=12
  • D6=12
  • DI=9
  • DMUX=15
  • DQ=3
  • DX=12
SLICEX
  • A=1226
  • A1=790
  • A2=1104
  • A3=1647
  • A4=1988
  • A5=2030
  • A6=1998
  • AMUX=500
  • AQ=2488
  • AX=1375
  • B=1185
  • B1=501
  • B2=716
  • B3=1235
  • B4=1490
  • B5=1646
  • B6=1658
  • BMUX=439
  • BQ=1913
  • BX=1034
  • C=758
  • C1=594
  • C2=811
  • C3=1155
  • C4=1421
  • C5=1489
  • C6=1457
  • CE=676
  • CLK=2945
  • CMUX=417
  • CQ=1846
  • CX=919
  • D=1054
  • D1=625
  • D2=798
  • D3=1154
  • D4=1516
  • D5=1593
  • D6=1574
  • DMUX=520
  • DQ=1670
  • DX=924
  • SR=1561
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -a -uc <fname>.ucf -p xc6slx150t-fgg900-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 105 103 0 0 0 0 0
bitgen 112 112 0 0 0 0 0
edif2ngd 1 1 0 0 0 0 0
map 163 120 0 0 0 0 0
ngcbuild 1 1 0 0 0 0 0
ngdbuild 187 187 0 0 0 0 0
par 120 113 4 0 0 0 0
trce 110 110 0 0 0 0 0
xst 144 141 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/7series/libs_le_ibufds.htm ( 2 ) /doc/usenglish/isehelp/7series/libs_le_mmcme2_base.htm ( 1 )
/doc/usenglish/isehelp/cgn_c_cust_gui_overview.htm ( 1 ) /doc/usenglish/isehelp/spartan6/libs_le_bscan_spartan6.htm ( 1 )
/doc/usenglish/isehelp/spartan6/libs_le_startup_spartan6.htm ( 1 ) /doc/usenglish/isehelp/spartan6/libs_le_suspend_sync.htm ( 1 )
/doc/usenglish/isehelp/sse_db_obsolete_symbols.htm ( 1 )
 
Project Statistics
PROPEXT_xilxMapPackRegInto_spartan6=For Inputs and Outputs PROP_CompxlibOverwriteLib=true
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PostTrceFastPath=false
PROP_PreTrceFastPath=false PROP_PropSpecInProjFile=Store all values
PROP_ReduceControlSets_spartan6=No PROP_SelectedInstanceHierarchicalPath=/testbench/uut
PROP_SimModelInsertBuffersPulseSwallow=false PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthOptEffort=High PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=Schematic PROP_UseSmartGuide=false
PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2011-02-04T13:02:17 PROP_intWbtProjectID=5791F61FD98743B7987AE3F307838D55
PROP_intWbtProjectIteration=14 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.mpc1
PROP_xilxBitgCfg_Code=0x04122017 PROP_xilxBitgCfg_EnableExternalMasterClk_spartan6=true
PROP_xilxBitgCfg_GenOpt_Compress=true PROP_xilxBitgCfg_Rate_spartan6=26
PROP_xilxBitgSusWake_EnGlblSetReset_spartan6=true PROP_xilxMapCoverMode=Speed
PROP_xilxNgdbldIOPads=true PROP_xstCrossClockAnalysis=true
PROP_xstEquivRegRemoval=false PROP_xstLUTCombining_spartan6=No
PROP_xstPackIORegister=Yes PROP_AutoTop=true
PROP_CompxlibSmartModels=true PROP_DevFamily=Spartan6
PROP_MapExtraEffort_spartan6=Normal PROP_MapRegDuplication_spartan6=On
PROP_xilxBitgCfg_GenOpt_BinaryFile=true PROPEXT_xilxPARextraEffortLevel_spartan6=Normal
PROP_CompxlibSimPath=changed PROP_DevDevice=xc6slx150t
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=fgg900
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=VHDL FILE_COREGEN=5
FILE_SCHEMATIC=1 FILE_UCF=1
FILE_VERILOG=4 FILE_VHDL=41
 
Power Data
Customer
Customer=TBD Customer Class=TBD
Device
Family=Spartan6 Die=xc6slx150t Package=fgg900 Speedgrade=-3
Tool Data
version=13.4 platform=win CPU=1 mins 12 secs Peak Memory=447 MB
Tool=ise Num run=1
Power Settings
Temp grade=C-Grade Process=Typical Settings file=No Simulation file=None
Simu_net_matched=NA Netlist_net_matched=NA PCF file=Yes Pct_clock_constrained=12
Pct_inputs_defined=0 User_junc_temp=0.0 Ambient temp=25.0 User effective thetaJA=NA
Airflow=0 heatsink=None User ThetaSA=NA Board selection=Medium (10x10)
Board layers=8 to 11 User ThetaJB=NA User Board Temp=NA Junction temp=57.9
Num run=1
Tool Defaults
Input toggle=12.5 Output toggle=12.5 Output enable=100.0 Bi-dir toggle=12.5
Bidir output enable=100.0 Output load=5.0 FF toggle=12.5 ram enable=25.0
ram write=50.0 DSP output toggle=12.5 Set/Reset probability=1.0 Set/Reset toggle=1.0
Enable probability=99.0 Enable toggle=1.0
Power Results
On-chip power=2320.21 Effective ThetaJA=14.2 ThetaSA=0.0 ThetaJB=6.5
Off-chip power=0.10
Thermal Power
Logic=11.89 Signal=55.90 Clock=305.48 BRAM=23.67
DSP=0.00 PLL=0.00 MMCM=0.00 PCIE=0.00
IO=249.80 GTX=1323.51 DevStatic=290.23
Supply Power
Vccint voltage=1.20 Vccint total current=898.56 Vccint static current=149.29 Vccint dynamic current=749.28
Vccaux voltage=2.50 Vccaux total current=51.56 Vccaux static current=45.89 Vccaux dynamic current=5.68
Vcco33 voltage=3.30 Vcco33 total current=70.47 Vcco33 static current=29.50 Vcco33 dynamic current=40.97
MGTAVcc voltage=1.20 MGTAVcc total current=191.43 MGTAVcc static current=14.00 MGTAVcc dynamic current=177.43
MGTAVccpll voltage=1.20 MGTAVccpll total current=375.15 MGTAVccpll static current=8.00 MGTAVccpll dynamic current=367.15
MGTAVtttx voltage=1.20 MGTAVtttx total current=157.22 MGTAVtttx static current=157.22 MGTAVtttx dynamic current=0.00
MGTAVttrx voltage=1.20 MGTAVttrx total current=10.00 MGTAVttrx static current=10.00 MGTAVttrx dynamic current=0.00
 
Core Statistics
Core Type=chipscope_icon_v1_06_a
c_build_revision=0 c_constraint_type=external c_core_major_ver=1 c_core_minor_alpha_ver=97
c_core_minor_ver=2 c_core_type=1 c_example_design=false c_major_version=14
c_mfg_id=1 c_minor_version=7 c_num_control_ports=1 c_part_idcode_register=0
c_use_bufr=0 c_use_control0=1 c_use_control1=0 c_use_control10=0
c_use_control11=0 c_use_control12=0 c_use_control13=0 c_use_control14=0
c_use_control2=0 c_use_control3=0 c_use_control4=0 c_use_control5=0
c_use_control6=0 c_use_control7=0 c_use_control8=0 c_use_control9=0
c_use_ext_bscan=0 c_use_jtag_bufg=1 c_use_new_parser=0 c_use_sim=0
c_use_softbscan=0 c_use_unused_bscan=0 c_use_xst_tck_workaround=1 c_user_scan_chain=1
c_xco_list=Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false c_xdevicefamily=spartan6
Core Type=chipscope_ila_v1_05_a
c_build_revision=0 c_constraint_type=external c_core_major_ver=1 c_core_minor_alpha_ver=97
c_core_minor_ver=4 c_core_type=2 c_data_depth=1024 c_data_width=1
c_example_design=false c_ext_cap_pin_mode=0 c_ext_cap_rate_mode=0 c_ext_cap_use_reg=1
c_m0_tpid=0 c_m0_type=1 c_m10_tpid=10 c_m10_type=0
c_m11_tpid=11 c_m11_type=0 c_m12_tpid=12 c_m12_type=0
c_m13_tpid=13 c_m13_type=0 c_m14_tpid=14 c_m14_type=0
c_m15_tpid=15 c_m15_type=0 c_m1_tpid=1 c_m1_type=0
c_m2_tpid=2 c_m2_type=0 c_m3_tpid=3 c_m3_type=0
c_m4_tpid=4 c_m4_type=0 c_m5_tpid=5 c_m5_type=0
c_m6_tpid=6 c_m6_type=0 c_m7_tpid=7 c_m7_type=0
c_m8_tpid=8 c_m8_type=0 c_m9_tpid=9 c_m9_type=0
c_major_version=14 c_mcnt0_width=1 c_mcnt10_width=1 c_mcnt11_width=1
c_mcnt12_width=1 c_mcnt13_width=1 c_mcnt14_width=1 c_mcnt15_width=1
c_mcnt1_width=1 c_mcnt2_width=1 c_mcnt3_width=1 c_mcnt4_width=1
c_mcnt5_width=1 c_mcnt6_width=1 c_mcnt7_width=1 c_mcnt8_width=1
c_mcnt9_width=1 c_mfg_id=1 c_minor_version=7 c_num_ext_cap_pins=8
c_num_match_units=1 c_num_tseq_cnt=0 c_num_tseq_states=1 c_ram_type=1
c_srl16_type=2 c_tc_mcnt_width=1 c_timestamp_depth=512 c_timestamp_type=0
c_timestamp_width=32 c_trig0_width=18 c_trig10_width=1 c_trig11_width=1
c_trig12_width=1 c_trig13_width=1 c_trig14_width=1 c_trig15_width=1
c_trig1_width=1 c_trig2_width=1 c_trig3_width=1 c_trig4_width=1
c_trig5_width=1 c_trig6_width=1 c_trig7_width=1 c_trig8_width=1
c_trig9_width=1 c_tseq_cnt0_width=1 c_tseq_cnt1_width=1 c_tseq_type=0
c_use_atc_clkin=0 c_use_data=0 c_use_gap=0 c_use_inv_clk=0
c_use_mcnt0=0 c_use_mcnt1=0 c_use_mcnt10=0 c_use_mcnt11=0
c_use_mcnt12=0 c_use_mcnt13=0 c_use_mcnt14=0 c_use_mcnt15=0
c_use_mcnt2=0 c_use_mcnt3=0 c_use_mcnt4=0 c_use_mcnt5=0
c_use_mcnt6=0 c_use_mcnt7=0 c_use_mcnt8=0 c_use_mcnt9=0
c_use_rpm=0 c_use_storage_qual=1 c_use_tc_mcnt=0 c_use_trig0=1
c_use_trig1=0 c_use_trig10=0 c_use_trig11=0 c_use_trig12=0
c_use_trig13=0 c_use_trig14=0 c_use_trig15=0 c_use_trig2=0
c_use_trig3=0 c_use_trig4=0 c_use_trig5=0 c_use_trig6=0
c_use_trig7=0 c_use_trig8=0 c_use_trig9=0 c_use_trig_out=0
c_use_trigdata0=1 c_use_trigdata1=0 c_use_trigdata10=0 c_use_trigdata11=0
c_use_trigdata12=0 c_use_trigdata13=0 c_use_trigdata14=0 c_use_trigdata15=0
c_use_trigdata2=0 c_use_trigdata3=0 c_use_trigdata4=0 c_use_trigdata5=0
c_use_trigdata6=0 c_use_trigdata7=0 c_use_trigdata8=0 c_use_trigdata9=0
c_xco_list=Component_Name=ILAP;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=1;Use_RPMs=false;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=1024;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=18;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=8;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic_with_edges;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=8;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic_with_edges;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=8;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic_with_edges;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=8;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic_with_edges;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=8;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic_with_edges;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=8;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic_with_edges;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=8;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic_with_edges;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=8;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic_with_edges;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=8;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic_with_edges;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=8;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic_with_edges;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=8;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic_with_edges;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=8;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic_with_edges;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=8;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic_with_edges;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=8;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic_with_edges;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=8;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic_with_edges;Exclude_From_Data_Storage_16=false c_xdevicefamily=spartan6
Core Type=fifo_generator_v6_2
c_common_clock=0 c_data_count_width=9 c_din_width=8 c_dout_rst_val=0
c_dout_width=8 c_enable_rst_sync=1 c_error_injection_type=0 c_full_flags_rst_val=1
c_has_almost_empty=0 c_has_almost_full=0 c_has_data_count=0 c_has_int_clk=0
c_has_overflow=0 c_has_rd_data_count=0 c_has_rst=1 c_has_srst=0
c_has_underflow=0 c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0
c_implementation_type=2 c_memory_type=1 c_msgon_val=1 c_overflow_low=0
c_preload_latency=1 c_preload_regs=0 c_prim_fifo_type=512x36 c_prog_empty_thresh_assert_val=2
c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_full_thresh_assert_val=509 c_prog_full_thresh_negate_val=508
c_prog_full_type=0 c_rd_data_count_width=9 c_rd_depth=512 c_rd_freq=1
c_rd_pntr_width=9 c_underflow_low=0 c_use_dout_rst=1 c_use_ecc=0
c_use_embedded_reg=0 c_use_fwft_data_count=0 c_valid_low=0 c_wr_ack_low=0
c_wr_data_count_width=9 c_wr_depth=512 c_wr_freq=1 c_wr_pntr_width=9
Core Type=chipscope_vio_v1_05_a
c_async_in_width=8 c_async_out_width=8 c_build_revision=0 c_constraint_type=external
c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=2 c_core_type=9
c_example_design=false c_major_version=14 c_mfg_id=1 c_minor_version=7
c_srl16_type=2 c_sync_in_width=8 c_sync_out_width=1 c_use_async_in=0
c_use_async_out=0 c_use_inv_clk=0 c_use_sync_in=0 c_use_sync_out=1
c_xco_list=Component_Name=mpcx_tx_vio;Enable_Synchronous_Input_Port=false;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=8;Synchronous_Output_Port_Width=1;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false c_xdevicefamily=spartan6
Core Type=chipscope_icon_v1_06_a
c_build_revision=0 c_constraint_type=external c_core_major_ver=1 c_core_minor_alpha_ver=97
c_core_minor_ver=2 c_core_type=1 c_example_design=false c_major_version=14
c_mfg_id=1 c_minor_version=7 c_num_control_ports=1 c_part_idcode_register=0
c_use_bufr=0 c_use_control0=1 c_use_control1=0 c_use_control10=0
c_use_control11=0 c_use_control12=0 c_use_control13=0 c_use_control14=0
c_use_control2=0 c_use_control3=0 c_use_control4=0 c_use_control5=0
c_use_control6=0 c_use_control7=0 c_use_control8=0 c_use_control9=0
c_use_ext_bscan=0 c_use_jtag_bufg=1 c_use_new_parser=0 c_use_sim=0
c_use_softbscan=0 c_use_unused_bscan=0 c_use_xst_tck_workaround=1 c_user_scan_chain=1
c_xco_list=Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false c_xdevicefamily=spartan6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=8 NGDBUILD_NUM_AND3=2 NGDBUILD_NUM_BSCAN_SPARTAN6=2 NGDBUILD_NUM_BUF=78
NGDBUILD_NUM_BUFG=12 NGDBUILD_NUM_DCM_SP=3 NGDBUILD_NUM_FD=2975 NGDBUILD_NUM_FDC=3162
NGDBUILD_NUM_FDCE=2194 NGDBUILD_NUM_FDE=393 NGDBUILD_NUM_FDP=594 NGDBUILD_NUM_FDPE=168
NGDBUILD_NUM_FDR=489 NGDBUILD_NUM_FDRE=92 NGDBUILD_NUM_FDS=402 NGDBUILD_NUM_FD_1=576
NGDBUILD_NUM_GND=47 NGDBUILD_NUM_GTPA1_DUAL=4 NGDBUILD_NUM_IBUF=382 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_IBUFGDS=10 NGDBUILD_NUM_INV=487 NGDBUILD_NUM_IOBUF=16 NGDBUILD_NUM_LDC=11
NGDBUILD_NUM_LUT1=512 NGDBUILD_NUM_LUT2=1491 NGDBUILD_NUM_LUT3=1068 NGDBUILD_NUM_LUT4=2282
NGDBUILD_NUM_LUT5=1141 NGDBUILD_NUM_LUT6=2254 NGDBUILD_NUM_MUXCY=1602 NGDBUILD_NUM_MUXCY_L=88
NGDBUILD_NUM_MUXF7=12 NGDBUILD_NUM_MUXF8=2 NGDBUILD_NUM_NAND2=2 NGDBUILD_NUM_NOR4=4
NGDBUILD_NUM_OBUF=106 NGDBUILD_NUM_OBUFDS=5 NGDBUILD_NUM_OBUFT=3 NGDBUILD_NUM_ODDR2=9
NGDBUILD_NUM_OR2=30 NGDBUILD_NUM_OR3=12 NGDBUILD_NUM_OR4=1 NGDBUILD_NUM_RAMB16BWER=1
NGDBUILD_NUM_RAMB8BWER=43 NGDBUILD_NUM_SRL16=18 NGDBUILD_NUM_SRL16E=1 NGDBUILD_NUM_SRLC16E=12
NGDBUILD_NUM_SRLC32E=35 NGDBUILD_NUM_VCC=47 NGDBUILD_NUM_XORCY=541
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=8 NGDBUILD_NUM_AND3=2 NGDBUILD_NUM_BSCAN_SPARTAN6=2 NGDBUILD_NUM_BUF=78
NGDBUILD_NUM_BUFG=12 NGDBUILD_NUM_DCM_SP=3 NGDBUILD_NUM_FD=2975 NGDBUILD_NUM_FDC=3162
NGDBUILD_NUM_FDCE=2194 NGDBUILD_NUM_FDE=393 NGDBUILD_NUM_FDP=594 NGDBUILD_NUM_FDPE=168
NGDBUILD_NUM_FDR=489 NGDBUILD_NUM_FDRE=92 NGDBUILD_NUM_FDS=402 NGDBUILD_NUM_FD_1=576
NGDBUILD_NUM_GND=89 NGDBUILD_NUM_GTPA1_DUAL=4 NGDBUILD_NUM_IBUF=403 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_IBUFGDS=10 NGDBUILD_NUM_INV=487 NGDBUILD_NUM_LDC=11 NGDBUILD_NUM_LUT1=512
NGDBUILD_NUM_LUT2=1491 NGDBUILD_NUM_LUT3=1068 NGDBUILD_NUM_LUT4=2282 NGDBUILD_NUM_LUT5=1141
NGDBUILD_NUM_LUT6=2254 NGDBUILD_NUM_MUXCY=1602 NGDBUILD_NUM_MUXCY_L=88 NGDBUILD_NUM_MUXF7=12
NGDBUILD_NUM_MUXF8=2 NGDBUILD_NUM_NAND2=2 NGDBUILD_NUM_NOR4=4 NGDBUILD_NUM_OBUF=106
NGDBUILD_NUM_OBUFDS=5 NGDBUILD_NUM_OBUFT=19 NGDBUILD_NUM_ODDR2=9 NGDBUILD_NUM_OR2=30
NGDBUILD_NUM_OR3=12 NGDBUILD_NUM_OR4=1 NGDBUILD_NUM_PULLUP=304 NGDBUILD_NUM_RAMB16BWER=1
NGDBUILD_NUM_RAMB8BWER=43 NGDBUILD_NUM_SRL16E=19 NGDBUILD_NUM_SRLC16E=12 NGDBUILD_NUM_SRLC32E=35
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=89 NGDBUILD_NUM_XORCY=541
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx150t-3-fgg900
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=YES -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Off -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=True -equivalent_register_removal=NO -slice_utilization_ratio_maxmargin=5