//    November 6, 2008 
//
// read IDCODE/USERCODE from xilinx XC2V4000 FPGA on TMB2005 board over jtag
// JTAG chain: TDI -> XC2V4000 -> XC18V04 -> XC18V04 -> XC18V04 -> XC18V04 -> TDO
// TMB2005 slot = 18 in the peripheral crate (boot register address 970000hex)
// bit_0 = tdi, bit_1 = tms, bit_2 = tck, bit_15 = tdo

// set test_logic/reset mode 5 times
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set run_test/idle mode
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set select_dr_scan mode
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set select_ir_scan mode
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set capture_ir_scan mode
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir_scan mode
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

//--------------------------------------------------
// send bypass instruction '11111111' to XC18V04 PROM_1
// set instruction bit 0
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 5
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 6
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 7
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

//--------------------------------------------------
// send bypass instruction '11111111' to XC18V04 PROM_2
// set instruction bit 0
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 5
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 6
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 7
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

//--------------------------------------------------
// send bypass instruction '11111111' to XC18V04 PROM_3
// set instruction bit 0
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 5
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 6
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 7
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

//--------------------------------------------------
// send bypass instruction '11111111' to XC18V04 PROM_4
// set instruction bit 0
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 5
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 6
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 7 
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// send instruction = '001001' = idcode = 11050093(hex) to XC2V4000 FPGA
// send instruction = '001000' = usercode to XC2V4000 EPROM

// set instruction bit 0
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 1
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 2
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 3
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a5);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a1);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 4
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set instruction bit 5 + tms = 1
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set update_ir
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set select_dr_scan
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set capture_dr
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_0 (invalid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da1=Data&0x8000;
	Da1 = Da1 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_1 (invalid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da2=Data&0x8000;
	Da2 = Da2 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_3 (invalid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da3=Data&0x8000;
	Da3 = Da3 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_4 (invalid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da4=Data&0x8000;
	Da4 = Da4 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_5 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da5=Data&0x8000;
	Da5 = Da5 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_6 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da6=Data&0x8000;
	Da6 = Da6 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_7 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da7=Data&0x8000;
	Da7 = Da7 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_8 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da8=Data&0x8000;
	Da8 = Da8 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_9 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da9=Data&0x8000;
	Da9 = Da9 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_10 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da10=Data&0x8000;
	Da10 = Da10 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_11 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da11=Data&0x8000;
	Da11 = Da11 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_12 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
  	Da12=Data&0x8000;
	Da12 = Da12 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_13 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
  	Da13=Data&0x8000;
	Da13 = Da13 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_14 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da14=Data&0x8000;
	Da14 = Da14 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_15 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da15=Data&0x8000;
	Da15 = Da15 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_16 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
  	Da16=Data&0x8000;
	Da16 = Da16 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_17 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da17=Data&0x8000;
	Da17 = Da17 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_18 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da18=Data&0x8000;
	Da18 = Da18 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_19 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da19=Data&0x8000;
	Da19 = Da19 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_20 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da20=Data&0x8000;
	Da20 = Da20 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_21 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da21=Data&0x8000;
	Da21 = Da21 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_22 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da22=Data&0x8000;
	Da22 = Da22 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_23 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da23=Data&0x8000;
	Da23 = Da23 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_24 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da24=Data&0x8000;
	Da24 = Da24 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_25 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da25=Data&0x8000;
	Da25 = Da25 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_26 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da26=Data&0x8000;
	Da26 = Da26 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_27 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da27=Data&0x8000;
	Da27 = Da27 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_28 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da28=Data&0x8000;
	Da28 = Da28 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_29 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da29=Data&0x8000;
	Da29 = Da29 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_30 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da30=Data&0x8000;
	Da30 = Da30 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_31 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da31=Data&0x8000;
	Da31 = Da31 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_32 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da32=Data&0x8000;
	Da32 = Da32 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_33 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da33=Data&0x8000;
	Da33 = Da33 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_34 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da34=Data&0x8000;
	Da34 = Da34 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_35 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da35=Data&0x8000;
	Da35 = Da35 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// set shift_ir bit_36 (valid)
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a4);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);
    vme->Read((bt_devaddr_t)0x970000, (WORD*)&Data);
 	Da36=Data&0x8000;
	Da36 = Da36 >> 15;
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

	cout << " XC2V4000 IDCODE = " << Da36 << Da35 << Da34 << Da33 << Da32 << Da31 << Da30 << Da29 << "_" 
		<< Da28 << Da27 << Da26	<< Da25 << Da24 << Da23 << Da22 << Da21 << "_" 
		<< Da20 << Da19 << Da18	<< Da17 << Da16 << Da15 << Da14 << Da13 << "_"
		<< Da12 << Da11 << Da10	<< Da9 <<  Da8 << Da7 << Da6 << Da5 << endl;	

// set updata_dr
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a6);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a2);
	vme->Write((bt_devaddr_t)0x970000, (WORD)0x00a0);

// end read back an idcode from XC2V4000 FPGA