User's Guide
Clock and Control Board
CCB'2004 for the EMU Peripheral and Track Finder Electronics, Production Version (October 2004)
Board Status (Location, Firmware,
Hardware, Mezzanines)
CCB'2004 for the EMU Peripheral and Track Finder Electronics, Preproduction Version (January 2004)
- CCB'2004 Specification. Version 2.0, 12/24/2004
- Configuration files .mcs and
.svf for the XC18V02VQ44 EPROM. Version 12/24/2004.
- Configuration files .mcs and
.svf for the XC18V02VQ44 EPROM. Version 10/13/2004 (added:
expanded to 500 ns Hard_reset, CSRB18, "Reset TTCrx" command).
- Configuration files .mcs and
.svf for the XC18V02VQ44 EPROM. Version 03/25/2004.
- CCB'2004 Schematic (pdf files)
CCB'2001 for the EMU Peripheral and Track Finder Electronics
- CCB'2001 Specification. Version 2.2, 08/04/2006
- CCB'2001 .pof file for the EPC2 EPROM. Version 12/09/2002
- CCB'2001 .pof file for the EPC2 EPROM. Version 02/01/2003
- CCB Schematic (pdf files)
- TTCrx Manual. Version 3.10, August 2005
- QPLL Manual. Version 1.1, 10 January 2005
- Clock Propagation Delays over EMU Peripheral Backplane.
Version 05/09/2002
- Jitter Measurements with a TTCrx ASIC, 03/18/2002
- Irradiation Test of the CCB, 02/27/2002
- CCB'2001 Block Diagram. Version 01/16/2002
-
CCB'2001 Backplane connector drawing (.dxf file)
- Pin assignment for the boards in the EMU peripheral crate.
A.Madorsky, 3 March 2001.
-
CSC Track Finder Crate Specification. A.Madorsky, 12 December 2002.
- General Information on TTC System (CERN RD12)
-
CMS L1 Trigger Control System. CMS Note 2002/033
-
Summary of Timing and Control Signals. Working document Version 24.10.2000
-
B.Taylor. Timing Distribution at the LHC. Presented at the
8th Workshop on Electronics for LHC Experiments, Colmar, France, 9-13 September 2002
- TTCvi-MkII Manual. Rev.1.6, May 2000.
- TTCvx Technical Description and Users Manual. May 21, 1999.
- TTCrq Mezzanine Card. Users Manual, Revision 0.1, February 2003.
- TTCmi Machine Interface. Users Manual, Rev. 1.3
-
Philips PCF8584 I2C Bus Controller. Specification and programming tips
- Example of TTCrx programming using PCF8584 (.txt file)
Software to run
TTCvi and TTCvx modules under VME control
Developed by Karol Bunkowski
of Warsaw University. Tested in March'2002 at Rice University with the Model 617
and Model 618 PCI-to-VME Bus Adapters
from SBS Technologies and CCB'2001 for
EMU Peripheral Electronics.
- TTCviCPP.zip contains C++ source files with TTCvi class (TTCviN.h file),
which provides all functions needed to control TTCvi board and connected
to it TTCrx boards. It also contains VME classes that are used to talk to
VME via Bit3 interface (Bit 3 Model 983 support software)
(files TVMEInterface.h and TVMEWinBit3.h).
- ConsoleTTCvi.zip contains the Microsoft Visual C++ project with the consol
application that sets TTCvi for sending commands required by CCB.
It may be treated as an example of using TTCvi class. With some small
changes it should be possible to compile the files with any other C++ compilator.
- WinTTCvi.zip contains Windows GUI application (TTCContr.exe) that gives
full control over TTCvi board.
CCB'99 for the EMU Peripheral Electronics
This is a first prototype of the CCB designed in 1999 for communication
with the TMB'99, CLCT'99 and ALCT'99 prototype boards.
CCB'2000 for the Track Finder crate
This is the first prototype of the CCB for the CSC Track Finder crate.
Three boards were built in summer 2000 and used at the University of Florida,
UCLA and Rice for joint test of the Sector Receiver and Sector Processor
modules. Will be replaced by the CCB'2001.
Muon Port Card
The MPC resides in the middle of the peripheral EMU crate and receives
trigger primitives from 9 or 8 Trigger Motherboards (designed at UCLA).
MPC'2002 selects three best patterns out of 18 (or 16) and transmits them
over three optical links to new combined Sector Receiver/Sector Processor
board (designed at the University of Florida).
MPC2004 for the EMU Peripheral Electronics (Production Version, February 2005)
Board Status (Location, Firmware,
Hardware, Mezzanines)
- MPC'2004 Specification. Version 02/12/2007
(Board_ID[5..0] and Link_ID[1..0] added,
CSR7 and CSR8 added to mask/unmask individually any LCT from any TMB, sorting scheme was changed to allow
zero-quality LCT's with vpf=1 to participate in sorting)
-
Configuration mcs file for the XC18V04 EPROM. Version 10/27/2006
(including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 participate in sorting)
-
Configuration svf file for the XC18V04 EPROM.
Version 10/27/2006 includes the Board_ID[5..0] + Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1
participate in sorting.
- MPC'2004 Specification. Version 10/26/2006 (Board_ID[5..0] and Link_ID[1..0] added,
CSR7 and CSR8 added to mask/unmask individually any LCT from any TMB)
- Configuration mcs file for the XC18V04 EPROM. Version 10/26/2006
(including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 do not participate in sorting)
- Configuration svf file for the XC18V04 EPROM.
Version 10/26/2006 (including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8,
zero-quality LCT's with vpf=1 do not participate in sorting).
- MPC'2004 Specification. Version 04/26/2006 (Board_ID[5..0] and Link_ID[1..0] added)
- Configuration mcs file for the XC18V04 EPROM. Version 04/26/2006
(including Board_ID[5..0] and Link_ID[1..0])
- Configuration svf file for the XC18V04 EPROM.
Version 04/26/2006 (including Board_ID[5..0] and Link_ID[1..0]).
- MPC'2004 Specification. Version 11/24/2005 (Including transparent BC0)
- Configuration mcs file for the XC18V04 EPROM. Version 11/24/2005
(Including transparent BC0)
- Configuration svf file for the XC18V04 EPROM. Version 11/24/2005
(Including transparent BC0)
- Configuration mcs file for the XC18V04 EPROM. Version 10/20/2005
- Configuration svf file to program XC18V04 EPROM. Version 10/20/2005
- Configuration svf file to verify XC18V04 EPROM. Version 10/20/2005
- Configuration mcs file for the XC18V04 EPROM. Version 04/23/2005
- Configuration svf file to program XC18V04 EPROM. Version 04/23/2005
- Configuration svf file to verify XC18V04 EPROM. Version 04/23/2005
- Configuration svf file to erase XC18V04 EPROM. Version 04/23/2005
- MPC2004 Schematic (pdf files)
- MPC2004 special project with the LFSR-based 15-bit PRBS generators for the optical links.
Identical PRBS generators for all three links. PRBS generators run continuously after power cycling.
Links need to be initialized by sending the L1Reset command.
The generators are reset by the BC0 pulse which is transmitted as a 16th bit
in the datastream from the MPC to SP. Interface to TMBs, sorter unit, FIFO_A and FIFO_B are not available.
- mcs file for XC18V04 EPROM
- svf file for the XC18V04 EPROM
- Simplified block diagram of the transmitter and receiver PRBS logic.
BC0 in the transmitter part here is a 12.5 ns pulse derived from the 25 ns BC0 TTC command.
- Firmware for the MPC2004, version 05/20/2008. Same as 10/27/2006, plus 16-bit L1Reset counter
added. Available for read (base address + B4). Reset on "FPGA Soft Reset command.
- Configuration mcs file for the XC18V04 EPROM. Version 05/20/2008
- Configuration svf file for the XC18V04 EPROM. Version 05/20/2008.
- MPC2004 Xilinx project
(zip) . Version 10/27/2006 (open with Xilinx ISE 6.2.03).
MPC'2002 for the EMU Peripheral Electronics (Initial Prototype, April 2002)
MPC'2000 for the EMU Peripheral Electronics
This is the first prototype of MPC designed in 2000. The board is able to
receive up to six trigger primitives from three Trigger Motherboards TMB'99,
select three best and transmit them to Sector Receiver prototype designed
at UCLA in 2000. The boards were used at the University of Florida for joint
tests with a prototypes of Sector Receiver and Sector Processor modules.
Muon Sorter
Muon Sorter receives up to 36 reconstructed muon primitives from
12 Sector Processors, selects the four best and transmits them to the Global Muon
Trigger crate for further processing. Muon Sorter resides in the middle
of the Track Finder crate and communicates with the Clock and Control Board (CCB) and Sector Processors
over custom backplane.
MS2005 (Modified Version, July 2005)
Board Status (Location, Firmware, Hardware,
Mezzanines)
- MS2005 Specification. Version 1.3, 06/26/2007
- Configuration files (.mcs) for XC18V04
EPROM1,
EPROM2,
EPROM3,
EPROM4,
version 06/26/2007 (same functionality as version 07/31/2006, but more flexible
control of the output RAM).
- Configuration
svf file for all four XC18V04 EPROMs, version 06/26/2007.
- MS2005 Specification. Version 1.2, 03/01/2007
- Configuration files (.mcs) for XC18V04
EPROM1,
EPROM2,
EPROM3,
EPROM4,
version 07/31/2006 (same functionality as version 11/11/2005, but reduced latency = 125 ns)
- Configuration files (.mcs) for XC18V04
EPROM1,
EPROM2,
EPROM3,
EPROM4,
version 11/11/2005 (latency = 150 ns)
- Configuration files (.mcs) for XC18V04
EPROM1,
EPROM2,
EPROM3,
EPROM4,
version 08/17/2005
- Erase EPROM's
svf file for all four XC18V04 EPROMs, version 11/11/2005
- Configuration
svf file for all four XC18V04 EPROMs, version 07/31/2006
- Configuration
svf file for all four XC18V04 EPROMs, version 11/11/2005
- Configuration
svf file for all four XC18V04 EPROMs, version 08/16/2005
- Configuration
evf file for all four XC18V04 EPROMs, version 08/16/2005
- Programming jed file for Xilinx XCR3128XL PLD, version 08/17/2005
- MS2005 Schematic (pdf files)
-
Specification of the MS-to-GMT non-halogen copper cable
- MS2005 Xilinx FPGA project
(zip) . Version 06/26/2007 (open with Xilinx ISE 6.2.03).
- MS2005 Xilinx PLD project
(zip) . Version 08/16/2005 (open with Xilinx ISE 6.2.03).
MS2003 (First Version, February 2003)
- Muon Sorter Specification. Version 2.1, 11/19/2004
(with four output RAM buffers)
- Muon Sorter Specification. Version 2.0, 05/04/2004
- Configuration files (.mcs) for XC18V04
EPROM1,
EPROM2,
EPROM3,
EPROM4,
version 06/16/2004 (modified data format to GMT, modified "winner" bits to SP)
- Configuration files (.svf) for XC18V04
all 4 EPROM's,
EPROM1,
EPROM2,
EPROM3,
EPROM4,
version 06/16/2004
- Configuration files (.mcs) for XC18V04
EPROM1,
EPROM2,
EPROM3,
EPROM4,
version 12/10/2003
MS Schematic (pdf files)
EPROM Configuration file (.evf)
for SCANPSC100F controller, version 12/10/2003
Configuration file (.jed) for XCR3128XL PLD, version 11/05/2003
Fairchild SCANPSC100FSC JTAG Controller
Mechanical Drawing of
the backplane connectors, 12/06/2002
CSC Track Finder Crate Specification. December 2002.
Specification if the Interface Between the Regional
Muon Triggers and the Global Muon Trigger. CMS Internal Note IN 2004/022 Version 1.00. June 8, 2004
Muon Tester Board
Muon Tester board is intended for testing of the CCB, MPC and MS boards.
Optoboard160
This board was built in the fall of 2005 and intended for evaluation of the
Texas Instruments TLK3101 gigabit transceivers and Finisar FTRJ8524
optical modules operating at 160MHz.
Evaluation Optoboard
This board was built in spring 2001 and intended for evaluation of the
Texas Instruments TLK2501 gigabit transceivers and Finisar FTRJ-8519
optical modules.
